Added HCLK and HRESETn

wally-pipelined/src/ahblite.sv

@@ -49,6 +49,7 @@ module ahblite (
   // AHB-Lite external signals
   input  logic [`AHBW-1:0] HRDATA,
   input  logic             HREADY, HRESP,
+  output logic             HCLK, HRESETn,
   output logic [31:0]      HADDR, 
   output logic [`AHBW-1:0] HWDATA,
   output logic             HWRITE, 
@@ -59,7 +60,6 @@ module ahblite (
   output logic             HMASTLOCK
 );
 
-  logic HCLK, HRESETn;
   logic GrantData;
   logic [2:0] ISize;
   logic [`AHBW-1:0] HRDATAMasked;
@@ -82,7 +82,7 @@ module ahblite (
   assign HADDR = GrantData ? DPAdrM[31:0] : IPAdrD[31:0];
   assign HWDATA = DWDataM;
   //flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
-  assign HWRITE = DWriteM; // *** check no level to pulse conversion needed
+  assign HWRITE = DWriteM; 
   assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize;
   assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT
   assign HPROT = 4'b0011; // not used; see Section 3.7

wally-pipelined/src/clint.sv

@@ -27,7 +27,7 @@
 `include "wally-config.vh"
 
 module clint (
-  input  logic             clk, reset, 
+  input  logic             HCLK, HRESETn,
   input  logic [1:0]       MemRWclint,
   input  logic [15:0]      HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
@@ -66,8 +66,8 @@ module clint (
           default:  HREADCLINT = 0;
         endcase
       end 
-      always_ff @(posedge clk or posedge reset) 
+      always_ff @(posedge HCLK or negedge HRESETn) 
-        if (reset) begin
+        if (~HRESETn) begin
           MSIP <= 0;
           MTIME <= 0;
           MTIMECMP <= 0;
@@ -90,8 +90,8 @@ module clint (
           default:  HREADCLINT = 0;
         endcase
       end 
-      always_ff @(posedge clk or posedge reset) 
+      always_ff @(posedge HCLK or negedge HRESETn) 
-        if (reset) begin
+        if (~HRESETn) begin
           MSIP <= 0;
           MTIME <= 0;
           MTIMECMP <= 0;

wally-pipelined/src/csrc.sv

@@ -182,9 +182,8 @@ module csrc #(parameter
                   IllegalCSRCAccessM = 1;
                 end
               endcase
-            end else 
+            end else begin 
-            begin 
+              IllegalCSRCAccessM = 1; // no privileges for this csr
-                 IllegalCSRCAccessM = 1; // no privileges for this coute
               CSRCReadValM = 0;
             end
         else // 32-bit counter reads
@@ -220,9 +219,8 @@ module csrc #(parameter
                   IllegalCSRCAccessM = 1;
                 end
               endcase
-            end else 
+            end else begin 
-            begin 
+              IllegalCSRCAccessM = 1; // no privileges for this csr
-                 IllegalCSRCAccessM = 1; // no privileges for this coute
               CSRCReadValM = 0;
             end
     end else begin

wally-pipelined/src/dtim.sv

@@ -26,24 +26,24 @@
 `include "wally-config.vh"
 
 module dtim (
-  input  logic            clk, 
+  input  logic             HCLK, HRESETn, 
   input  logic [1:0]       MemRWtim,
-//  input  logic [7:0]      ByteMaskM,
   input  logic [18:0]      HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
+  input  logic             HSELTim,
   output logic [`XLEN-1:0] HREADTim,
   output logic             HRESPTim, HREADYTim
 );
 
   logic [`XLEN-1:0] RAM[0:65535];
-  logic [`XLEN-1:0] write;
+//  logic [`XLEN-1:0] write;
   logic [15:0] entry;
   logic            memread, memwrite;
 
   assign memread = MemRWtim[1];
   assign memwrite = MemRWtim[0];
   assign HRESPTim = 0; // OK
-  assign HREADYTim= 1; // Respond immediately; *** extend this 
+  assign HREADYTim = 1; // Respond immediately; *** extend this 
   
   // word aligned reads
   generate
@@ -87,12 +87,15 @@ module dtim (
     end
   endgenerate */
   generate
-    if (`XLEN == 64) begin
+    if (`XLEN == 64) 
-      always_ff @(posedge clk)
+      always_ff @(posedge HCLK) begin
         if (memwrite) RAM[HADDR[17:3]] <= HWDATA;  
-    end else begin
+//        HREADTim <= RAM[HADDR[17:3]];
-      always_ff @(posedge clk)
+      end
+    else 
+      always_ff @(posedge HCLK) begin
         if (memwrite) RAM[HADDR[17:2]] <= HWDATA;  
+//        HREADTim <= RAM[HADDR[17:2]];
       end
   endgenerate
 endmodule

wally-pipelined/src/gpio.sv

@@ -28,7 +28,7 @@
 `include "wally-config.vh"
 
 module gpio (
-  input  logic             clk, reset, 
+  input  logic             HCLK, HRESETn,
   input  logic [1:0]       MemRWgpio,
   input  logic [7:0]       HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
@@ -75,8 +75,8 @@ module gpio (
           default:  HREADGPIO = 0;
         endcase
       end 
-      always_ff @(posedge clk or posedge reset) 
+      always_ff @(posedge HCLK or negedge HRESETn) 
-        if (reset) begin
+        if (~HRESETn) begin
           INPUT_EN <= 0;
           OUTPUT_EN <= 0;
           OUTPUT_VAL <= 0; // spec indicates synchronous reset (software control)
@@ -96,8 +96,8 @@ module gpio (
           default:  HREADGPIO = 0;
         endcase
       end 
-      always_ff @(posedge clk or posedge reset) 
+      always_ff @(posedge HCLK or negedge HRESETn) 
-        if (reset) begin
+        if (~HRESETn) begin
           INPUT_EN <= 0;
           OUTPUT_EN <= 0;
           //OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)

wally-pipelined/src/uart.sv

@@ -28,7 +28,7 @@
 `include "wally-config.vh"
 
 module uart (
-  input  logic            clk, reset, 
+  input  logic            HCLK, HRESETn, 
   input  logic [1:0]      MemRWuart,
   input  logic [2:0] HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
@@ -79,6 +79,7 @@ module uart (
   endgenerate
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
+  // *** make sure reads don't occur on UART unless fully selected because they could change state.  This applies to all peripherals
   uartPC16550D u(.RCLK(BAUDOUTb), .*);
 
 endmodule

wally-pipelined/src/uartPC16550D.sv

@@ -34,7 +34,7 @@
 
 module uartPC16550D(
   // Processor Interface
-  input  logic       clk, reset,
+  input  logic       HCLK, HRESETn,
   input  logic [2:0] A,
   input  logic [7:0] Din,
   output logic [7:0] Dout,
@@ -112,7 +112,7 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // Input synchronization: 2-stage synchronizer
   ///////////////////////////////////////////
-  always_ff @(posedge clk) begin
+  always_ff @(posedge HCLK) begin
     {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb};
     {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
         {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
@@ -122,8 +122,8 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // Register interface (Table 1, note some are read only and some write only)
   ///////////////////////////////////////////
-  always_ff @(posedge clk, posedge reset) 
+  always_ff @(posedge HCLK, negedge HRESETn) 
-    if (reset) begin // Table 3 Reset Configuration
+    if (~HRESETn) begin // Table 3 Reset Configuration
       IER <= 4'b0;
       FCR <= 8'b0;
       LCR <= 8'b0;
@@ -184,8 +184,8 @@ module uartPC16550D(
   // Unlike PC16550D, this unit is hardwired with same rx and tx baud clock
   // *** add table of scale factors to get 16x uart clk
   ///////////////////////////////////////////
-  always_ff @(posedge clk, posedge reset) 
+  always_ff @(posedge HCLK, negedge HRESETn) 
-    if (reset) begin
+    if (~HRESETn) begin
       baudcount <= 0;
       baudpulse <= 0;
     end else begin
@@ -200,8 +200,8 @@ module uartPC16550D(
   // receive timing and control
   ///////////////////////////////////////////
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge HCLK, negedge HRESETn)
-    if (reset) begin
+    if (~HRESETn) begin
       rxoversampledcnt <= 0;
       rxstate <= UART_IDLE;
       rxbitsreceived <= 0;
@@ -231,8 +231,8 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge HCLK, negedge HRESETn)
-    if (reset) rxshiftreg <= 0;
+    if (~HRESETn) rxshiftreg <= 0;
     else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit
   assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
   assign rxstopbit = rxshiftreg[0];
@@ -253,8 +253,8 @@ module uartPC16550D(
   assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
 
   // receive FIFO and register
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge HCLK, negedge HRESETn)
-    if (reset) begin
+    if (~HRESETn) begin
       rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0;
     end else begin
       if (rxstate == UART_DONE) begin
@@ -297,8 +297,8 @@ module uartPC16550D(
   assign rxfifohaserr = |(rxerrbit & rxfullbit);
 
   // receive buffer register and ready bit
-  always_ff @(posedge clk, posedge reset) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
+  always_ff @(posedge HCLK, negedge HRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (reset) rxfifodmaready <= 0;
+    if (~HRESETn) rxfifodmaready <= 0;
     else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1;
     else if (rxfifoempty) rxfifodmaready <= 0;
 
@@ -316,8 +316,8 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // transmit timing and control
   ///////////////////////////////////////////
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge HCLK, negedge HRESETn)
-    if (reset) begin
+    if (~HRESETn) begin
       txoversampledcnt <= 0;
       txstate <= UART_IDLE;
       txbitssent <= 0;
@@ -364,8 +364,8 @@ module uartPC16550D(
   end
        
   // registers & FIFO
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge HCLK, negedge HRESETn)
-    if (reset) begin
+    if (~HRESETn) begin
       txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 0;
     end else begin
       if (~MEMWb && A == 3'b000 && ~DLAB) begin // writing transmit holding register or fifo
@@ -404,8 +404,8 @@ module uartPC16550D(
   assign txfifofull = (txfifoentries == 4'b1111);
 
   // transmit buffer ready bit
-  always_ff @(posedge clk, posedge reset) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
+  always_ff @(posedge HCLK, negedge HRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (reset) txfifodmaready <= 0;
+    if (~HRESETn) txfifodmaready <= 0;
     else if (txfifoempty) txfifodmaready <= 1;
     else if (txfifofull)  txfifodmaready <= 0;
 
@@ -440,7 +440,7 @@ module uartPC16550D(
       intrpending = 0;
     end
   end
-  always @(posedge clk) INTR <= intrpending; // prevent glitches on interrupt pin
+  always @(posedge HCLK) INTR <= intrpending; // prevent glitches on interrupt pin
 
   ///////////////////////////////////////////
   // modem control logic

wally-pipelined/src/uncore.sv

@@ -29,8 +29,8 @@
 // *** need idiom to map onto cache RAM with byte writes
 // *** and use memread signal to reduce power when reads aren't needed
 module uncore (
-  input  logic            clk, reset,
   // AHB Bus Interface
+  input  logic             HCLK, HRESETn,
   input  logic [31:0]      HADDR,
   input  logic [`AHBW-1:0] HWDATAIN,
   input  logic             HWRITE,
@@ -76,6 +76,13 @@ module uncore (
   assign MemRWclint = MemRW & {2{HSELCLINT}};
   assign MemRWgpio = MemRW & {2{HSELGPIO}};
   assign MemRWuart = MemRW & {2{HSELUART}};
+/*  always_ff @(posedge HCLK) begin
+    HADDRD <= HADDR;
+    MemRWtim  <= MemRW & {2{HSELTim}};
+    MemRWclint <= MemRW & {2{HSELCLINT}};
+    MemRWgpio  <= MemRW & {2{HSELGPIO}};
+    MemRWuart  <= MemRW & {2{HSELUART}};
+  end */
 
   // subword accesses: converts HWDATAIN to HWDATA
   subwordwrite sww(.*);

wally-pipelined/src/wallypipelinedhart.sv

@@ -37,6 +37,7 @@ module wallypipelinedhart (
   // Bus Interface
   input  logic [`AHBW-1:0] HRDATA,
   input  logic             HREADY, HRESP,
+  output logic             HCLK, HRESETn,
   output logic [31:0]      HADDR,
   output logic [`AHBW-1:0] HWDATA,
   output logic             HWRITE,

wally-pipelined/src/wallypipelinedsoc.sv

@@ -38,6 +38,7 @@ module wallypipelinedsoc (
   input  logic [`AHBW-1:0] HRDATAEXT,
   input  logic             HREADYEXT, HRESPEXT,
   // outputs to external memory, shared with uncore memory
+  output logic             HCLK, HRESETn,
   output logic [31:0]      HADDR,
   output logic [`AHBW-1:0] HWDATA,
   output logic             HWRITE,

wally-pipelined/testbench/testbench-imperas.sv

@@ -230,6 +230,7 @@ string tests32i[] = {
   logic [3:0]       HPROT;
   logic [1:0]       HTRANS;
   logic             HMASTLOCK;
+  logic             HCLK, HRESETn;
 
   
   // pick tests based on modes supported