forked from Github_Repos/cvw
Name changes for states in LSU.
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13b4201198
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@ -455,8 +455,8 @@ module lsu
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assign NextFetchCount = FetchCount + 1'b1;
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assign NextFetchCount = FetchCount + 1'b1;
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typedef enum {STATE_BUS_READY,
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typedef enum {STATE_BUS_READY,
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STATE_BUS_FETCH_WDV,
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STATE_BUS_FETCH,
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STATE_BUS_WRITE_WDV,
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STATE_BUS_WRITE,
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STATE_BUS_UNCACHED_WRITE,
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STATE_BUS_UNCACHED_WRITE,
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STATE_BUS_UNCACHED_WRITE_DONE,
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STATE_BUS_UNCACHED_WRITE_DONE,
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STATE_BUS_UNCACHED_READ,
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STATE_BUS_UNCACHED_READ,
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@ -500,13 +500,13 @@ module lsu
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end
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end
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// D$ Fetch Line
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// D$ Fetch Line
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else if(DCFetchLine) begin
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else if(DCFetchLine) begin
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BusNextState = STATE_BUS_FETCH_WDV;
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BusNextState = STATE_BUS_FETCH;
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CntReset = 1'b1;
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CntReset = 1'b1;
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BusStall = 1'b1;
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BusStall = 1'b1;
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end
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end
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// D$ Write Line
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// D$ Write Line
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else if(DCWriteLine) begin
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else if(DCWriteLine) begin
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BusNextState = STATE_BUS_WRITE_WDV;
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BusNextState = STATE_BUS_WRITE;
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CntReset = 1'b1;
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CntReset = 1'b1;
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BusStall = 1'b1;
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BusStall = 1'b1;
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end
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end
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@ -544,7 +544,7 @@ module lsu
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SelUncached = 1'b1;
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SelUncached = 1'b1;
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end
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end
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STATE_BUS_FETCH_WDV: begin
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STATE_BUS_FETCH: begin
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BusStall = 1'b1;
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BusStall = 1'b1;
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PreCntEn = 1'b1;
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PreCntEn = 1'b1;
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DCtoAHBReadM = 1'b1;
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DCtoAHBReadM = 1'b1;
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@ -554,11 +554,11 @@ module lsu
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BusNextState = STATE_BUS_READY;
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BusNextState = STATE_BUS_READY;
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BUSACK = 1'b1;
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BUSACK = 1'b1;
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end else begin
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end else begin
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BusNextState = STATE_BUS_FETCH_WDV;
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BusNextState = STATE_BUS_FETCH;
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end
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end
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end
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end
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STATE_BUS_WRITE_WDV: begin
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STATE_BUS_WRITE: begin
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BusStall = 1'b1;
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BusStall = 1'b1;
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PreCntEn = 1'b1;
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PreCntEn = 1'b1;
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DCtoAHBWriteM = 1'b1;
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DCtoAHBWriteM = 1'b1;
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@ -567,7 +567,7 @@ module lsu
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BusNextState = STATE_BUS_READY;
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BusNextState = STATE_BUS_READY;
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BUSACK = 1'b1;
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BUSACK = 1'b1;
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end else begin
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end else begin
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BusNextState = STATE_BUS_WRITE_WDV;
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BusNextState = STATE_BUS_WRITE;
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end
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end
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end
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end
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endcase
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endcase
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