Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

.gitignore

@@ -1,6 +1,8 @@
 **/work*
 **/wally_*.log
 
+.nfs*
+
 #vsim work files to ignore
 transcript
 vsim.wlf

wally-pipelined/src/uncore/imem.sv

@@ -53,19 +53,11 @@ module imem (
   generate 
     if (`XLEN==32) begin
       assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
-      if(`TIMBASE==0) begin
-        assign InstrAccessFaultF = 0;
-      end else begin
-        assign InstrAccessFaultF = ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF
-      end
+      assign InstrAccessFaultF = ~&(({AdrF,0} ~^ `TIMBASE) | `TIMRANGE);
     end else begin
       assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
                           : (AdrF[1] ? rd[47:16] : rd[31:0]);
-      if(`TIMBASE==0) begin
-        assign InstrAccessFaultF = 0;
-      end else begin
-        assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF]
-      end
+      assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE);
     end
   endgenerate
 endmodule