Changed names of Icache signals.

wally-pipelined/regression/wave.do

@@ -175,11 +175,11 @@ add wave -noupdate -group icache -expand -group {fsm out and control} /testbench
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/IfuBusFetch
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
 add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
@@ -187,7 +187,7 @@ add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
-add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/IfuBusFetch
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn

wally-pipelined/src/cache/icache.sv

@@ -37,11 +37,11 @@ module icache
    input logic 				  ExceptionM, PendingInterruptM,
   
    // Data read in from the ebu unit
-   (* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF,
+   (* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA,
-   (* mark_debug = "true" *) input logic InstrAckF,
+   (* mark_debug = "true" *) input logic ICacheBusAck,
    // Read requested from the ebu unit
-   (* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF,
+   (* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
-   (* mark_debug = "true" *) output logic InstrReadF,
+   (* mark_debug = "true" *) output logic IfuBusFetch,
    // High if the instruction currently in the fetch stage is compressed
    output logic 			  CompressedF,
    // High if the icache is requesting a stall
@@ -77,7 +77,7 @@ module icache
   // Input signals to cache memory
   logic 					  ICacheMemWriteEnable;
   logic [BLOCKLEN-1:0] 		  ICacheMemWriteData;
-  logic [`PA_BITS-1:0] 		  PCTagF;  
+  logic [`PA_BITS-1:0] 		  FinalPCPF;  
   // Output signals from cache memory
   logic [31:0] 				  ICacheMemReadData;
   logic 					  ICacheReadEn;
@@ -111,7 +111,7 @@ module icache
 
   logic [31:0] 				  ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0];
   
-  logic [`PA_BITS-1:0] 		  BasePAdrF, BasePAdrMaskedF;
+  logic [`PA_BITS-1:0] 		  BasePAdrMaskedF;
   logic [OFFSETLEN-1:0] 	  BasePAdrOffsetF;
   
   
@@ -121,7 +121,7 @@ module icache
   // on spill we want to get the first 2 bytes of the next cache block.
   // the spill only occurs if the PCPF mod BlockByteLength == -2.  Therefore we can
   // simply add 2 to land on the next cache block.
-  assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
+  assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; 
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
@@ -134,7 +134,7 @@ module icache
   cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
 			 .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
   MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
-					  .PAdr(PCTagF),
+					  .PAdr(FinalPCPF),
 					  .WriteEnable(SRAMWayWriteEnable),
 					  .VDWriteEnable(1'b0),
 					  .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
@@ -154,7 +154,7 @@ module icache
       cachereplacementpolicy(.clk, .reset,
 							 .WayHit,
 							 .VictimWay,
-							 .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+							 .LsuPAdrM(FinalPCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 							 .RAdr,
 							 .LRUWriteEn);
     end else begin
@@ -177,7 +177,7 @@ module icache
 	assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
   endgenerate
 
-  assign ICacheMemReadData = ReadLineSetsF[PCTagF[$clog2(BLOCKLEN / 32) + 1 : 1]];
+  assign ICacheMemReadData = ReadLineSetsF[FinalPCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
   
   // spills require storing the first cache block so it can merged
   // with the second
@@ -216,8 +216,8 @@ module icache
     for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
       flopenr #(`XLEN) sb(.clk(clk),
 						  .reset(reset), 
-						  .en(InstrAckF & (i == FetchCount)),
+						  .en(ICacheBusAck & (i == FetchCount)),
-						  .d(InstrInF),
+						  .d(IfuBusHRDATA),
 						  .q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]));
     end
   endgenerate
@@ -231,17 +231,14 @@ module icache
 						 .d(SelAdr[1]),
 						 .q(SelAdr_q[1]));
   
-  assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF;
+  assign FinalPCPF = SelAdr_q[1] ? PCPSpillF : PCPF;
-
-  // unlike the dcache the victim is never dirty so no eviction is necessary.
-  assign BasePAdrF = PCTagF;
 
   // if not cacheable the offset bits needs to be sent to the EBU.
   // if cacheable the offset bits are discarded.  $ FSM will fetch the whole block.
-  assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : BasePAdrF[OFFSETLEN-1:0];
+  assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
-  assign BasePAdrMaskedF = {BasePAdrF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
+  assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
   
-  assign InstrPAdrF = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
+  assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
   
   // truncate the offset from PCPF for memory address generation
 
@@ -257,8 +254,8 @@ module icache
 						.ITLBWriteF,
 						.ExceptionM,
 						.PendingInterruptM,
-						.InstrAckF,
+						.ICacheBusAck,
-						.InstrReadF,
+						.IfuBusFetch,
 						.hit,
 						.FetchCountFlag,
 						.spill,

wally-pipelined/src/cache/icachefsm.sv

@@ -38,7 +38,7 @@ module icachefsm
    input logic 		  ExceptionM, PendingInterruptM,
 
    // BUS interface
-   input logic 		  InstrAckF,
+   input logic 		  ICacheBusAck,
 
    // icache internal inputs
    input logic 		  hit,
@@ -54,7 +54,7 @@ module icachefsm
    output logic 	  ICacheStallF,
 
    // Bus interface outputs
-   output logic 	  InstrReadF,
+   output logic 	  IfuBusFetch,
 
    // icache internal outputs
    output logic 	  spillSave,
@@ -121,7 +121,7 @@ module icachefsm
   always_comb begin
     CntReset = 1'b0;
     PreCntEn = 1'b0;
-    //InstrReadF = 1'b0;
+    //IfuBusFetch = 1'b0;
     ICacheMemWriteEnable = 1'b0;
     spillSave = 1'b0;
     SelAdr = 2'b00;
@@ -186,9 +186,9 @@ module icachefsm
       end
       STATE_HIT_SPILL_MISS_FETCH_WDV: begin
         SelAdr = 2'b10;
-        //InstrReadF = 1'b1;
+        //IfuBusFetch = 1'b1;
         PreCntEn = 1'b1;
-        if (FetchCountFlag & InstrAckF) begin
+        if (FetchCountFlag & ICacheBusAck) begin
           NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
         end else begin
           NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
@@ -221,9 +221,9 @@ module icachefsm
       // branch 3 miss no spill
       STATE_MISS_FETCH_WDV: begin
         SelAdr = 2'b01;
-        //InstrReadF = 1'b1;
+        //IfuBusFetch = 1'b1;
         PreCntEn = 1'b1;
-        if (FetchCountFlag & InstrAckF) begin
+        if (FetchCountFlag & ICacheBusAck) begin
           NextState = STATE_MISS_FETCH_DONE;	  
         end else begin
           NextState = STATE_MISS_FETCH_WDV;
@@ -256,8 +256,8 @@ module icachefsm
       STATE_MISS_SPILL_FETCH_WDV: begin
         SelAdr = 2'b01;
         PreCntEn = 1'b1;
-        //InstrReadF = 1'b1;	
+        //IfuBusFetch = 1'b1;	
-        if (FetchCountFlag & InstrAckF) begin 
+        if (FetchCountFlag & ICacheBusAck) begin 
           NextState = STATE_MISS_SPILL_FETCH_DONE;
         end else begin
           NextState = STATE_MISS_SPILL_FETCH_WDV;
@@ -300,8 +300,8 @@ module icachefsm
       STATE_MISS_SPILL_MISS_FETCH_WDV: begin
         SelAdr = 2'b10;
         PreCntEn = 1'b1;
-        //InstrReadF = 1'b1;	
+        //IfuBusFetch = 1'b1;	
-        if (FetchCountFlag & InstrAckF) begin
+        if (FetchCountFlag & ICacheBusAck) begin
           NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;	  
         end else begin
           NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
@@ -358,8 +358,8 @@ module icachefsm
     endcase
   end
 
-  assign CntEn = PreCntEn & InstrAckF;
+  assign CntEn = PreCntEn & ICacheBusAck;
-  assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
+  assign IfuBusFetch = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
 					  (CurrState == STATE_MISS_FETCH_WDV) ||
 					  (CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
 					  (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);

wally-pipelined/src/ebu/ahblite.sv

@@ -40,10 +40,10 @@ module ahblite (
   input logic 				 UnsignedLoadM,
   input logic [1:0] 		 AtomicMaskedM,
   // Signals from Instruction Cache
-  input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
+  input logic [`PA_BITS-1:0] ICacheBusAdr, // *** rename these to match block diagram
-  input logic 				 InstrReadF,
+  input logic 				 IfuBusFetch,
-  output logic [`XLEN-1:0] 	 InstrRData,
+  output logic [`XLEN-1:0] 	 IfuBusHRDATA,
-  output logic 				 InstrAckF,
+  output logic 				 ICacheBusAck,
   // Signals from Data Cache
   input logic [`PA_BITS-1:0] LsuBusAdr,
   input logic 				 LsuBusRead, 
@@ -100,23 +100,23 @@ module ahblite (
     case (BusState) 
       IDLE: if (LsuBusRead)      NextBusState = MEMREAD;  // Memory has priority over instructions
             else if (LsuBusWrite)NextBusState = MEMWRITE;
-            else if (InstrReadF)   NextBusState = INSTRREAD;
+            else if (IfuBusFetch)   NextBusState = INSTRREAD;
             else                   NextBusState = IDLE;
       MEMREAD: if (~HREADY)        NextBusState = MEMREAD;
-            else if (InstrReadF)   NextBusState = INSTRREAD;
+            else if (IfuBusFetch)   NextBusState = INSTRREAD;
             else                   NextBusState = IDLE;
       MEMWRITE: if (~HREADY)       NextBusState = MEMWRITE;
-            else if (InstrReadF)   NextBusState = INSTRREAD;
+            else if (IfuBusFetch)   NextBusState = INSTRREAD;
             else                   NextBusState = IDLE;
       INSTRREAD: if (~HREADY)      NextBusState = INSTRREAD;
-            else                   NextBusState = IDLE;  // if (InstrReadF still high)
+            else                   NextBusState = IDLE;  // if (IfuBusFetch still high)
       default:                     NextBusState = IDLE;
     endcase
 
 
   //  bus outputs
   assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
-  assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0];
+  assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : ICacheBusAdr[31:0];
   assign #1 HADDR = AccessAddress;
   assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
   assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
@@ -136,9 +136,9 @@ module ahblite (
   // *** assumes AHBW = XLEN
 
  
-  assign InstrRData = HRDATA;
+  assign IfuBusHRDATA = HRDATA;
   assign LsuBusHRDATA = HRDATA;
-  assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
+  assign ICacheBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
   assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
 
 endmodule

wally-pipelined/src/ifu/ifu.sv

@@ -31,11 +31,11 @@ module ifu (
   input logic 		      StallF, StallD, StallE, StallM, StallW,
   input logic 		      FlushF, FlushD, FlushE, FlushM, FlushW,
   // Fetch
-  input logic [`XLEN-1:0]     InstrInF,
+  input logic [`XLEN-1:0]     IfuBusHRDATA,
-  input logic 		      InstrAckF,
+  input logic 		      ICacheBusAck,
   (* mark_debug = "true" *) output logic [`XLEN-1:0]    PCF, 
-  output logic [`PA_BITS-1:0] InstrPAdrF,
+  output logic [`PA_BITS-1:0] ICacheBusAdr,
-  output logic 		      InstrReadF,
+  output logic 		      IfuBusFetch,
   output logic 		      ICacheStallF,
   // Execute
   output logic [`XLEN-1:0]    PCLinkE,
@@ -159,16 +159,16 @@ module ifu (
   
 
   // *** put memory interface on here, InstrF becomes output
-  //assign InstrPAdrF = PCF; // *** no MMU
+  //assign ICacheBusAdr = PCF; // *** no MMU
-  //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
+  //assign IfuBusFetch = ~StallD; // *** & ICacheMissF; add later
-  // assign InstrReadF = 1; // *** & ICacheMissF; add later
+  // assign IfuBusFetch = 1; // *** & ICacheMissF; add later
 
   // conditional
   // 1. ram // controlled by `MEM_IROM
   // 2. cache // `MEM_ICACHE
   // 3. wire pass-through
-  icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
+  icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .IfuBusHRDATA, .ICacheBusAck,
-  .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
+  .ICacheBusAdr, .IfuBusFetch, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
 				.CacheableF,
   .PCNextF(PCNextFPhys),
   .PCPF(PCPFmmu),

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -128,10 +128,10 @@ module wallypipelinedhart (
   logic 		    CommittedM;
 
   // AHB ifu interface
-  logic [`PA_BITS-1:0] 	    InstrPAdrF;
+  logic [`PA_BITS-1:0] 	    ICacheBusAdr;
-  logic [`XLEN-1:0] 	    InstrRData;
+  logic [`XLEN-1:0] 	    IfuBusHRDATA;
-  logic 		    InstrReadF;
+  logic 		    IfuBusFetch;
-  logic 		    InstrAckF;
+  logic 		    ICacheBusAck;
   
   // AHB LSU interface
   logic [`PA_BITS-1:0] 	    LsuBusAdr;
@@ -164,8 +164,8 @@ module wallypipelinedhart (
 
     .ExceptionM, .PendingInterruptM,
     // Fetch
-    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF,
+    .IfuBusHRDATA, .ICacheBusAck, .PCF, .ICacheBusAdr,
-    .InstrReadF, .ICacheStallF,
+    .IfuBusFetch, .ICacheStallF,
 
     // Execute
     .PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
@@ -277,8 +277,8 @@ module wallypipelinedhart (
   ahblite ebu(// IFU connections
      .clk, .reset,
      .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
-     .InstrPAdrF, // *** rename these to match block diagram
+     .ICacheBusAdr, // *** rename these to match block diagram
-     .InstrReadF, .InstrRData, .InstrAckF,
+     .IfuBusFetch, .IfuBusHRDATA, .ICacheBusAck,
      // Signals from Data Cache
      .LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
      .LsuBusHRDATA,