forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
99e3a0db28
@ -52,6 +52,9 @@
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`define ITLB_ENTRY_BITS 5
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`define DTLB_ENTRY_BITS 5
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 64'h0000000080000000
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@ -101,7 +104,7 @@
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
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`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE"//comments
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@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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#do ./wave-dos/linux-waves.do
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do ./wave-dos/linux-waves.do
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#-- Run the Simulation
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@ -474,18 +474,18 @@ module testbench();
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end
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string PCtextD,PCtextE,PCtextM,PCtext2;
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always_ff @(posedge clk, posedge reset)
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if (reset) begin
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PCtextE <= #1 "(reset)";
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PCtextM <= #1 "(reset)";
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end else begin
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if (~dut.hart.StallE)
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if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
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else PCtextE <= #1 PCtextD;
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if (~dut.hart.StallM)
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if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
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else PCtextM <= #1 PCtextE;
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end
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//always_ff @(posedge clk, posedge reset)
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// if (reset) begin
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// PCtextE <= #1 "(reset)";
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// PCtextM <= #1 "(reset)";
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// end else begin
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// if (~dut.hart.StallE)
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// if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
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// else PCtextE <= #1 PCtextD;
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// if (~dut.hart.StallM)
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// if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
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// else PCtextM <= #1 PCtextE;
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// end
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initial begin
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@ -498,10 +498,8 @@ module testbench();
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always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
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if(~HWRITE) begin
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#2;
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$display("test point");
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if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
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if (dut.hart.ifu.PCD !== lastPCD) begin
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$display("tp2");
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lastCheckInstrD = CheckInstrD;
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lastPC <= dut.hart.ifu.PCD;
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lastPC2 <= lastPC;
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@ -528,22 +526,16 @@ module testbench();
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end
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end
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else begin
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$display("tp4");
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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`ERROR
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end
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD);
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PCtext2 = "";
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$display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
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while (PCtext2 != "***") begin
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$display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
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PCtextD = {PCtextD, " ", PCtext2};
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$display("tp8");
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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$display("tp9");
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end
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$display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
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if(dut.hart.ifu.PCD === pcExpected) begin
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if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs
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