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Possible fix.

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This commit is contained in:
Ross Thompson 2022-08-28 13:10:47 -05:00
parent 5e77b1bd2b
commit 99e0e5c817
2 changed files with 2 additions and 2 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -194,7 +194,7 @@ module ifu (
assign IROMAdr = CPUBusy | reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS assign IROMAdr = CPUBusy | reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
adrdec iromdec(IROMAdr, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM); adrdec iromdec(PCFExt, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM);
assign NonIROMMemRWM = {~SelIROM, 1'b0}; assign NonIROMMemRWM = {~SelIROM, 1'b0};
irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF)); irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));

2
pipelined/src/lsu/lsu.sv
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@ -34,7 +34,7 @@
// cpubusy means the cpu is stalled and the lsu must ensure ReadDataM stalls constant until the stall is removed. // cpubusy means the cpu is stalled and the lsu must ensure ReadDataM stalls constant until the stall is removed.
// chap 5 handling faults to memory by delaying writes to memory stage. // chap 5 handling faults to memory by delaying writes to memory stage.
// chap 6 combing bus with dtim // chap 6 combing bus with dtim
// chap 9 complete lsu.
`include "wally-config.vh" `include "wally-config.vh"