removed false critical path from fpu

pipelined/src/fpu/flags.sv

@@ -24,14 +24,13 @@ module flags(
     input logic  [1:0]          NegResMSBS,             // the negitive integer result's most significant bits
     input logic                 ZSgnEffM, PSgnM,        // the product and modified Z signs
     input logic                 Round, UfLSBRes, Sticky, UfPlus1, // bits used to determine rounding
-    output logic                Invalid, Overflow, Underflow, // flags used to select the res
+    output logic                IntInvalid, Invalid, Overflow, Underflow, // flags used to select the res
     output logic [4:0]          PostProcFlgM // flags
 );
     logic               SigNaN;     // is an input a signaling NaN
     logic               Inexact;    // inexact flag
     logic               FpInexact;  // floating point inexact flag
     logic               IntInexact; // integer inexact flag
-    logic               IntInvalid; // integer invalid flag
     logic               FmaInvalid; // integer invalid flag
     logic               DivInvalid; // integer invalid flag
     logic               DivByZero;
@@ -112,7 +111,7 @@ module flags(
     //                  if the res is too small to be represented and not 0
     //                  |                                     and if the res is not invalid (outside the integer bounds)
     //                  |                                     |
-    assign IntInexact = ((CvtCalcExpM[`NE]&~XZeroM)|Sticky|Round)&~Invalid;
+    assign IntInexact = ((CvtCalcExpM[`NE]&~XZeroM)|Sticky|Round)&~IntInvalid;
 
     // select the inexact flag to output
     assign Inexact = ToInt ? IntInexact : FpInexact;
@@ -136,14 +135,14 @@ module flags(
     assign FmaInvalid = ((XInfM | YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);
     assign DivInvalid = ((XInfM & YInfM) | (XZeroM & YZeroM))&~Sqrt | (XSgnM&Sqrt);
 
-    assign Invalid = SigNaN | (FmaInvalid&FmaOp) | (DivInvalid&DivOp) | (IntInvalid&CvtOp&ToInt);
+    assign Invalid = SigNaN | (FmaInvalid&FmaOp) | (DivInvalid&DivOp);
 
 
     assign DivByZero = YZeroM&DivOp;  
 
     // Combine flags
     //      - to integer results do not set the underflow or overflow flags
-    assign PostProcFlgM = {Invalid, DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact};
+    assign PostProcFlgM = {Invalid|(IntInvalid&CvtOp&ToInt), DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact};
 
 endmodule
 

pipelined/src/fpu/postprocess.sv

@@ -85,7 +85,7 @@ module postprocess(
     logic [3*`NF+8:0]            ShiftIn;        // is the sum zero
     logic [`NORMSHIFTSZ-1:0]    Shifted;    // the shifted result
     logic                   Plus1;      // add one to the final result?
-    logic                   Overflow, Underflow, Invalid; // flags
+    logic                   IntInvalid, Overflow, Underflow, Invalid; // flags
     logic                   Signed;     // is the opperation with a signed integer?
     logic                   Int64;      // is the integer 64 bits?
     logic                   IntToFp;       // is the opperation an int->fp conversion?
@@ -187,7 +187,7 @@ module postprocess(
 
     flags flags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .InfIn, .XZeroM, .YZeroM, 
                 .XSgnM, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCalcExpM,
-                .XNaNM, .YNaNM, .NaNIn, .ZSgnEffM, .PSgnM, .Round,
+                .XNaNM, .YNaNM, .NaNIn, .ZSgnEffM, .PSgnM, .Round, .IntInvalid,
                 .UfLSBRes, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullResExp, .Plus1,
                 .RoundExp, .NegResMSBS, .Invalid, .Overflow, .Underflow, .PostProcFlgM);
 
@@ -195,7 +195,7 @@ module postprocess(
     // Select the result
     ///////////////////////////////////////////////////////////////////////////////
 
-    resultselect resultselect(.XSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZDenormM, .ZZeroM, .XZeroM,
+    resultselect resultselect(.XSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZDenormM, .ZZeroM, .XZeroM, .IntInvalid,
         .IntZeroM, .FrmM, .OutFmt, .AddendStickyM, .KillProdM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .CvtResUf, 
         .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .NegResMSBS,
         .FullResExp, .Shifted, .CvtCalcExpM, .ResSgn, .ResExp, .ResFrac, .PostProcResM, .FCvtIntResM);

pipelined/src/fpu/resultselect.sv

@@ -25,7 +25,7 @@ module resultselect(
     input logic 		            ZZeroM,
     input logic                     ResSgn,  // the res's sign
     input logic     [`FLEN:0]       RoundAdd,   // how much to add to the res
-    input logic                     Invalid, Overflow,  // flags
+    input logic                     IntInvalid, Invalid, Overflow,  // flags
     input logic CvtResUf,
     input logic     [`NE-1:0]       ResExp,          // Res exponent
     input logic     [`NE+1:0]       FullResExp,          // Res exponent
@@ -276,7 +276,7 @@ module resultselect(
     //          - if rounding and signed opperation and negitive input, output -1
     //          - otherwise output a rounded 0
     //      - otherwise output the normal res (trmined and sign extended if nessisary)
-    assign FCvtIntResM = Invalid ?  OfIntRes :
+    assign FCvtIntResM = IntInvalid ?  OfIntRes :
 			            CvtCalcExpM[`NE] ? XSgnM&Signed&Plus1 ? {{`XLEN{1'b1}}} : {{`XLEN-1{1'b0}}, Plus1} : //CalcExp has to come after invalid ***swap to actual mux at some point??
                         Int64 ? NegRes[`XLEN-1:0] : {{`XLEN-32{NegRes[31]}}, NegRes[31:0]};
 endmodule