Updated linux test bench documenation and scripts.

wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt

@@ -0,0 +1,38 @@
+Many of the scripts to build the linux ram.txt and trace files have changed over the Summer.
+Specifically the parsed*.txt files have all been replaced by a single all.txt file which contains
+all of the changes concurrent with a specific instruction.
+Each line of all.txt is encoded in the following way.
+
+The tokens are space deliminted (limitation the parsing function in system verilog).  This could be
+improved with some effort.
+
+<Token> denotes a required token.
+
+()? is an optional set of tokens.  Exactly 0 or 1 of this pattern will occur.
+The register update, memory operation, and CSR update are all possilbe but not present on all operations.
+()+ is used to denote a variable number of this pattern with at least 1 instance of the pattern.
+All integers are in hex and not zero extended.
+
+<PC> <instruction bits> <instruction text> (<GPR> <Reg Number> <Value>)? (<MemR|MemW|MemRW> <Address> <WriteData if valid> <ReadData if valid>)? (<CSR> (<Name> <Value>)+)?
+
+Example
+
+1010 182b283 ld_t0,24(t0) GPR 5 80000000 MemR 1018 0 80000000
+
+PC = 0x1010
+Instruction encoding = 0x182_b283
+instruction pneumonic (text) = ld_t0,24(t0)
+Updating x5 to 0x8000_0000
+Memory read at address 0x8000_0000 with read data of 0x8000_0000
+
+CSR updates can occur in more than once for a single instruction.  The multiple sets will appear as pairs of regsiter name followed by value.
+
+**** This trace is generated using the CreateTrace.sh script.
+
+Generation of ram.txt has not changed.  Still use logBuildrootMem.sh
+
+Only the all.txt and ram.txt are required to run modelsim's linux simulation. However there are three additional files will aid
+in the debugging process.  logBuildrootMem.sh was modified to also create an object dump from the vmlinux image.  Using
+extractFunctionRadix.sh the objdump is converted into two files vmlinux.objdump.addr and vmlinux.objdump.lab which contain
+the addresses and labels of global functions in the linux binarary. The linux test bench is configured to uses these two files
+to tell the user which function is currently being executed in modelsim.

wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh

@@ -5,14 +5,14 @@
 # You can run "tail -f nohup.out" to see what would've
 # outputted to the terminal if you didn't use nohup
 
-#customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
+# use on tera.
-customQemu="qemu-system-riscv64"
+customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
+# use on other systems
+#customQemu="qemu-system-riscv64"
 imageDir="../buildroot-image-output"
 intermedDir="../linux-testvectors/intermediate-outputs"
 outDir="../linux-testvectors"
 
 # - Logs info needed by buildroot testbench
-#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parseNew.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
-#./fix_csrs.py "$outDir"
 
 ($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > all.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog

wally-pipelined/linux-testgen/testvector-generation/logBuildrootMem.sh

@@ -1,7 +1,21 @@
+#!/bin/bash
+
+# use on tera.
 customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
+# use on other systems
+#customQemu="qemu-system-riscv64"
+
 imageDir="../buildroot-image-output"
+testVecDir="../linux-testvectors"
+
 ($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1235 -S 2>/dev/null >/dev/null) &
 riscv64-unknown-elf-gdb -x gdbinit_mem
 echo "Translating Mem from GDB to Questa format"
 ./fix_mem.py
 echo "Done"
+
+echo "Creating debugging objdump of linux image"
+
+riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $testVecDir/vmlinux.objdump
+extractFunctionRadix.sh $testVecDir/vmlinux.objdump
+echo "Done"

wally-pipelined/regression/linux-wave.do

@@ -6,6 +6,7 @@ add wave -noupdate /testbench/dut/hart/SATP_REGW
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
 add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
@@ -469,13 +470,9 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChang
 add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
 add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
 add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
-add wave -noupdate /testbench/FunctionName/FunctionAddr
-add wave -noupdate /testbench/FunctionName/FunctionName
-add wave -noupdate /testbench/FunctionName/ProgramAddrMapFile
-add wave -noupdate /testbench/FunctionName/ProgramLabelMapFile
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {39985218 ns} 0} {{Cursor 23} {8750281 ns} 0}
+WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {72228581 ns} 0} {{Cursor 23} {11297671 ns} 0}
-quietly wave cursor active 4
+quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 354
 configure wave -justifyvalue left
@@ -490,4 +487,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {9232357 ns}
+WaveRestoreZoom {72227242 ns} {72229920 ns}

wally-pipelined/regression/wally-buildroot.do

@@ -34,10 +34,11 @@ vopt +acc work.testbench -o workopt
 
 vsim workopt -suppress 8852,12070
 
+run 150 ms
 add log -r /*
 do linux-wave.do
 
-run 300 ms
+run 150 ms
 #run 180 us
 
 #-- Run the Simulation