Merge pull request #249 from davidharrishmc/dev

DV Test Plan, fdivsqrt, merged exclusions

docs/testplans/testplan.md

@@ -0,0 +1,29 @@
+# CORE-V Wally Test Plan
+
+CORE-V Wally is tested in the following ways:
+
+* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
+* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
+* ***pending: Run random tests generated by risc-dv
+* Run CoreMark and Embench benchmarks.
+* Run performance validation against reference models for the branch predictor and caches.
+* Run the TestFloat suite against all precisions of all operations for the FPU unit.
+* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
+* Boot Buildroot Linux in lock-step against ImperasDV.
+* Boot Buildroot Linux on an FPGA and run programs.
+
+# Running Tests
+
+# 
+
+# Detailed Test Plans
+
+The test plans for specific units are lined below:
+
+* Privileged Unit
+* Memory Management Unit
+* Peripherals
+* Branch Predictor Performance Validation
+* Cache Performance Validation
+
+Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  

sim/coverage-exclusions-rv64gc.do

@@ -34,6 +34,9 @@ do GetLineNum.do
 # This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
 coverage exclude -srcfile lzc.sv 
 
+# FDIVSQRT has 
+coverage exclude -scope /core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
+
 ### Exclude D$ states and logic for the I$ instance
 # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
 # Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
@@ -74,19 +77,6 @@ for {set i 0} {$i < $numcacheways} {incr i} {
     coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
 }
 
-######################
-# Toggle exclusions
-#   Not used because toggle coverage isn't measured
-######################
-
-# Exclude DivBusyE from all design units because rv64gc uses the fdivsqrt unit for integer division
-#coverage exclude -togglenode DivBusyE -du *
-# Exclude QuotM and RemM from MDU because rv64gc uses the fdivsqrt rather tha div unit for integer division
-#coverage exclude -togglenode /dut/core/mdu/mdu/QuotM
-#coverage exclude -togglenode /dut/core/mdu/mdu/RemM
-
-# StallFCause is hardwired to 0
-#coverage exclude -togglenode /dut/core/hzu/StallFCause
 
 # Excluding peripherals as sources of instructions for the ifu
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec

src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -71,6 +71,7 @@ module fdivsqrtfsm(
 // NS = NF + 1
 // N = NS or NS+2 for div/sqrt.  
 
+// *** CT 4/13/23 move cycles calculation back to preprocesor
 /* verilator lint_off WIDTH */
   logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
   if (`FPSIZES == 1)
@@ -110,7 +111,8 @@ module fdivsqrtfsm(
   always_ff @(posedge clk) begin
       if (reset | FlushE) begin
           state <= #1 IDLE; 
-      end else if ((state == IDLE) & IFDivStartE) begin 
+      end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
+//       end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
           step <= cycles; 
           if (SpecialCaseE) state <= #1 DONE;
           else              state <= #1 BUSY;

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -101,17 +101,19 @@ module fdivsqrtpreproc (
   lzc #(`DIVb) lzcX (IFX, ell);
   lzc #(`DIVb) lzcY (IFD, mE);
 
-  // Normalization shift
+  // Normalization shift: shift off leading one
-  assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
+  assign XPreproc = (IFX << ell) << 1;
-  assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
+  assign DPreproc = (IFD << mE)  << 1; 
 
-  // append leading 1 (for normal inputs)
+  // append leading 1 (for nonzero inputs)
   // shift square root to be in range [1/4, 1)
   // Normalized numbers are shifted right by 1 if the exponent is odd
   // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
   mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
   assign DivX = {3'b000, ~NumerZeroE, XPreproc};
+  // *** CT 4/13/23 Create D output here with leading 1 appended as well, use in the other modules
 
+  // ***CT: factor out fdivsqrtcycles
   if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
     logic [`DIVBLEN:0] ZeroDiff, p;
     logic  ALTBE;
@@ -119,7 +121,7 @@ module fdivsqrtpreproc (
     // calculate number of fractional bits p
     assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
     assign ALTBE = ZeroDiff[`DIVBLEN];  // A less than B (A has more leading zeros)
-    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p);            // *** is there a more graceful way to write these constants    
+    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);              
 
     // Integer special cases (terminate immediately)
     assign ISpecialCaseE = BZeroE | ALTBE;