Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Moved privileged pc logic into privileged unit.

Browse Source
This commit is contained in:
Ross Thompson 2022-12-20 17:55:45 -06:00
parent 35ad49502f
commit 97593e8a6f
4 changed files with 23 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
pipelined/src/ifu/ifu.sv
View File

@ -54,7 +54,8 @@ module ifu (
// Mem // Mem
input logic RetM, TrapM, input logic RetM, TrapM,
output logic CommittedF, output logic CommittedF,
input logic [`XLEN-1:0] PrivilegedNextPCM, input logic [`XLEN-1:0] UnalignedPCNextF,
output logic [`XLEN-1:0] PCNext2F,
input logic CSRWriteFenceM, input logic CSRWriteFenceM,
input logic InvalidateICacheM, input logic InvalidateICacheM,
output logic [31:0] InstrD, InstrM, output logic [31:0] InstrD, InstrM,
@ -85,7 +86,7 @@ module ifu (
output logic ICacheAccess, output logic ICacheAccess,
output logic ICacheMiss output logic ICacheMiss
); );
(* mark_debug = "true" *) logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
logic BranchMisalignedFaultE; logic BranchMisalignedFaultE;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
@ -116,7 +117,7 @@ module ifu (
logic GatedStallF; logic GatedStallF;
(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; (* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
// branch predictor signal // branch predictor signal
logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; logic [`XLEN-1:0] PCNext1F, PCNext0F;
logic BusCommittedF, CacheCommittedF; logic BusCommittedF, CacheCommittedF;
logic SelIROM; logic SelIROM;
@ -289,12 +290,7 @@ module ifu (
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F));
// mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F));
else assign PCNext2F = PCNext1F; else assign PCNext2F = PCNext1F;
if(`ZICSR_SUPPORTED) begin
logic PrivilegedChangePCM;
assign PrivilegedChangePCM = RetM | TrapM;
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM),
.y(UnalignedPCNextF));
end else assign UnalignedPCNextF = PCNext2F;
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);

10
pipelined/src/privileged/csr.sv
View File

@ -40,7 +40,7 @@ module csr #(parameter
input logic FlushE, FlushM, FlushW, input logic FlushE, FlushM, FlushW,
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F,
input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM, input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM,
input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
@ -70,7 +70,7 @@ module csr #(parameter
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW, output logic [2:0] FRM_REGW,
output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM, output logic [`XLEN-1:0] CSRReadValW, UnalignedPCNextF,
output logic IllegalCSRAccessM, BigEndianM output logic IllegalCSRAccessM, BigEndianM
); );
@ -100,6 +100,8 @@ module csr #(parameter
logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM;
logic MTrapM, STrapM; logic MTrapM, STrapM;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = ~StallW & ~FlushW; assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@ -149,6 +151,10 @@ module csr #(parameter
else if (mretM) PrivilegedNextPCM = MEPC_REGW; else if (mretM) PrivilegedNextPCM = MEPC_REGW;
else PrivilegedNextPCM = SEPC_REGW; else PrivilegedNextPCM = SEPC_REGW;
logic PrivilegedChangePCM;
assign PrivilegedChangePCM = mretM | sretM | TrapM;
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
/////////////////////////////////////////// ///////////////////////////////////////////
// CSRWriteValM // CSRWriteValM
/////////////////////////////////////////// ///////////////////////////////////////////

8
pipelined/src/privileged/privileged.sv
View File

@ -33,10 +33,10 @@ module privileged (
input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW,
(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] PCM, PCNext2F,
input logic [31:0] InstrM, input logic [31:0] InstrM,
output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] UnalignedPCNextF,
output logic RetM, TrapM, output logic RetM, TrapM,
output logic sfencevmaM, output logic sfencevmaM,
input logic InstrValidM, CommittedM, CommittedF, input logic InstrValidM, CommittedM, CommittedF,
@ -122,7 +122,7 @@ module privileged (
csr csr(.clk, .reset, csr csr(.clk, .reset,
.FlushE, .FlushM, .FlushW, .FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .IEUAdrM, .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .MTIME_CLINT,
@ -142,7 +142,7 @@ module privileged (
.PMPADDR_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.SetFflagsM, .SetFflagsM,
.FRM_REGW, .FRM_REGW,
.CSRReadValW,.PrivilegedNextPCM, .CSRReadValW,.UnalignedPCNextF,
.IllegalCSRAccessM, .BigEndianM); .IllegalCSRAccessM, .BigEndianM);
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,

12
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -69,7 +69,7 @@ module wallypipelinedcore (
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] CSRReadValW, MDUResultW; logic [`XLEN-1:0] CSRReadValW, MDUResultW;
logic [`XLEN-1:0] PrivilegedNextPCM; logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
(* mark_debug = "true" *) logic [1:0] MemRWM; (* mark_debug = "true" *) logic [1:0] MemRWM;
(* mark_debug = "true" *) logic InstrValidM; (* mark_debug = "true" *) logic InstrValidM;
logic InstrMisalignedFaultM; logic InstrMisalignedFaultM;
@ -173,7 +173,7 @@ module wallypipelinedcore (
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,
// Fetch // Fetch
.HRDATA, .PCF, .IFUHADDR, .HRDATA, .PCF, .IFUHADDR, .PCNext2F,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
.IFUHREADY, .IFUHWRITE, .IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
@ -183,7 +183,7 @@ module wallypipelinedcore (
.BPPredWrongE, .BPPredWrongE,
// Mem // Mem
.RetM, .TrapM, .CommittedF, .PrivilegedNextPCM, .InvalidateICacheM, .CSRWriteFenceM, .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
.InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM, .InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM,
.BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
@ -334,8 +334,8 @@ module wallypipelinedcore (
.clk, .reset, .clk, .reset,
.FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,
.StallD, .StallE, .StallM, .StallW, .StallD, .StallE, .StallM, .StallW,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
.InstrM, .CSRReadValW, .PrivilegedNextPCM, .InstrM, .CSRReadValW, .UnalignedPCNextF,
.RetM, .TrapM, .RetM, .TrapM,
.sfencevmaM, .sfencevmaM,
.InstrValidM, .CommittedM, .CommittedF, .InstrValidM, .CommittedM, .CommittedF,
@ -362,7 +362,7 @@ module wallypipelinedcore (
); );
end else begin end else begin
assign CSRReadValW = 0; assign CSRReadValW = 0;
assign PrivilegedNextPCM = 0; assign UnalignedPCNextF = PCNext2F;
assign RetM = 0; assign RetM = 0;
assign TrapM = 0; assign TrapM = 0;
assign wfiM = 0; assign wfiM = 0;