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Clarified interlockfsm.

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This commit is contained in:
Ross Thompson 2022-02-22 11:31:28 -06:00
parent 1ab2e7590b
commit 971dd494f6
2 changed files with 50 additions and 40 deletions
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25
pipelined/src/lsu/interlockfsm.sv
View File

@ -31,10 +31,11 @@
`include "wally-config.vh"
module interlockfsm
(input logic clk,
module interlockfsm(
input logic clk,
input logic reset,
input logic AnyCPUReqM,
input logic [1:0] MemRWM,
input logic [1:0] AtomicM,
input logic ITLBMissOrDAFaultF,
input logic ITLBWriteF,
input logic DTLBMissOrDAFaultM,
@ -48,6 +49,11 @@ module interlockfsm
output logic IgnoreRequestTLB,
output logic IgnoreRequestTrapM);
logic ToITLBMiss;
logic ToITLBMissNoReplay;
logic ToDTLBMiss;
logic ToBoth;
logic AnyCPUReqM;
typedef enum logic[2:0] {STATE_T0_READY,
STATE_T0_REPLAY,
@ -58,6 +64,11 @@ module interlockfsm
(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ToITLBMiss = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM;
assign ToITLBMissNoReplay = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM;
assign ToDTLBMiss = ~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
assign ToBoth = ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
always_ff @(posedge clk)
if (reset) InterlockCurrState <= #1 STATE_T0_READY;
@ -66,10 +77,10 @@ module interlockfsm
always_comb begin
case(InterlockCurrState)
STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY;
else if(~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS;
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;
else if(ToDTLBMiss) InterlockNextState = STATE_T3_DTLB_MISS;
else if(ToITLBMissNoReplay) InterlockNextState = STATE_T4_ITLB_MISS;
else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
else InterlockNextState = STATE_T0_READY;
STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T0_READY;

3
pipelined/src/lsu/lsuvirtmen.sv
View File

@ -78,13 +78,12 @@ module lsuvirtmem(
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
interlockfsm interlockfsm (
.clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
hptw hptw( // *** remove logic from (), mention this in style guide CH3