csr cleanup

pipelined/src/privileged/csrc.sv

@@ -10,6 +10,7 @@
 //          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
 // 
 // Documentation: RISC-V System on Chip Design Chapter 5
+//    MHPMEVENT is not supported
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -61,14 +62,14 @@ module csrc #(parameter
   output logic 	            IllegalCSRCAccessM
 );
 
-  logic [4:0]  CounterNumM;
+  logic [4:0]               CounterNumM;
-  (* mark_debug = "true" *)     logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
+  (* mark_debug = "true" *)  logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
-  logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
+  logic [`XLEN-1:0]         HPMCOUNTERH_REGW[`COUNTERS-1:0];
-  logic LoadStallE, LoadStallM;
+  logic                     LoadStallE, LoadStallM;
-  logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
+  logic [`COUNTERS-1:0]     WriteHPMCOUNTERM;
-  logic [`COUNTERS-1:0] CounterEvent;
+  logic [`COUNTERS-1:0]     CounterEvent;
-  logic [63:0]      HPMCOUNTERPlusM[`COUNTERS-1:0];
+  logic [63:0]              HPMCOUNTERPlusM[`COUNTERS-1:0];
-  logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:0];
+  logic [`XLEN-1:0]         NextHPMCOUNTERM[`COUNTERS-1:0];
   genvar i;
 
   // Interface signals
@@ -76,24 +77,24 @@ module csrc #(parameter
   flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));	
   
   // Determine when to increment each counter
-  assign CounterEvent[0] = 1'b1;  // MCYCLE always increments
+  assign CounterEvent[0] = 1'b1;                                                        // MCYCLE always increments
-  assign CounterEvent[1] = 1'b0;  // Counter 1 doesn't exist
+  assign CounterEvent[1] = 1'b0;                                                        // Counter 1 doesn't exist
-  assign CounterEvent[2] = InstrValidNotFlushedM;
+  assign CounterEvent[2] = InstrValidNotFlushedM;                                       // MINSTRET instructions retired
   if(`QEMU) begin: cevent // No other performance counters in QEMU
     assign CounterEvent[`COUNTERS-1:3] = 0;
-  end else begin: cevent // User-defined counters
+  end else begin: cevent                                                                // User-defined counters
-    assign CounterEvent[3] = LoadStallM;  // don't want to suppress on flush as this only happens if flushed.
+    assign CounterEvent[3] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;
+    assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;               // Branch predictor wrong direction
-    assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
+    assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
-    assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
+    assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
-    assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM;
+    assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions
-    assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
+    assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
-    assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;
+    assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
-    assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;
+    assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
-    assign CounterEvent[11] = DCacheAccess;
+    assign CounterEvent[11] = DCacheAccess;                                             // data cache access
-    assign CounterEvent[12] = DCacheMiss;
+    assign CounterEvent[12] = DCacheMiss;                                               // data cache miss
-    assign CounterEvent[13] = ICacheAccess;
+    assign CounterEvent[13] = ICacheAccess;                                             // instruction cache access
-    assign CounterEvent[14] = ICacheMiss;
+    assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss
     assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   
@@ -157,8 +158,4 @@ module csrc #(parameter
     end
 endmodule
 
-// To Do:
-//  review couunter spec
-//  upper unimplemented counters should read as 0 rather than illegal access
 //  mounteren should only exist if u-mode exists
-//  Implement MHPMEVENT

pipelined/src/privileged/csrm.sv

@@ -159,10 +159,12 @@ module csrm #(parameter
   flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
   flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
-  if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
+  if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration
   else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
   flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
+  if (`U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
+    flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
+  end else assign MCOUNTEREN_REGW = '0;
 
   // Read machine mode CSRs
   // verilator lint_off WIDTH

pipelined/testbench/testbench-linux.sv

@@ -152,7 +152,7 @@ module testbench;
   `define SCAUSE      `CSR_BASE.csrs.csrs.SCAUSEreg.q
   `define MEPC        `CSR_BASE.csrm.MEPCreg.q
   `define SEPC        `CSR_BASE.csrs.csrs.SEPCreg.q
-  `define MCOUNTEREN  `CSR_BASE.csrm.MCOUNTERENreg.q
+  `define MCOUNTEREN  `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q
   `define SCOUNTEREN  `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
   `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
   `define SSCRATCH    `CSR_BASE.csrs.csrs.SSCRATCHreg.q