forked from Github_Repos/cvw
mmu cleanup
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David Harris
parent
697a8d8f50
commit
939bf3f148
@ -24,76 +24,56 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
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parameter IMMU = 0) (
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module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
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input logic clk, reset,
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// Current value of satp CSR (from privileged unit)
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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// Current privilege level of the processeor
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input logic [1:0] PrivilegeModeW,
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// 00 - TLB is not being accessed
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// 1x - TLB is accessed for a read (or an instruction)
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// x1 - TLB is accessed for a write
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// 11 - TLB is accessed for both read and write
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input logic DisableTranslation,
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// VAdr is the virtual/physical address from IEU or physical address from HPTW.
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// PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr)
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// when there is translation.
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input logic [`XLEN+1:0] VAdr,
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input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
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// Controls for writing a new entry to the TLB
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageTypeWriteVal,
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input logic TLBWrite,
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// Invalidate all TLB entries
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input logic TLBFlush,
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// Physical address outputs
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output logic [`PA_BITS-1:0] PhysicalAddress,
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output logic TLBMiss,
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output logic Cacheable, Idempotent, SelTIM,
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input logic [`XLEN-1:0] SATP_REGW, // Current value of satp CSR (from privileged unit)
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // Status bits affecting translation
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input logic [1:0] STATUS_MPP, // previous machine privilege level
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input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
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input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
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input logic [`XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW
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input logic [1:0] Size, // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
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input logic [`XLEN-1:0] PTE, // page table entry
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input logic [1:0] PageTypeWriteVal, // page type
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input logic TLBWrite, // write TLB entry
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input logic TLBFlush, // Invalidate all TLB entries
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output logic [`PA_BITS-1:0] PhysicalAddress, // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
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output logic TLBMiss, // Miss TLB
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output logic Cacheable, // PMA indicates memory address is cachable
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output logic Idempotent, // PMA indicates memory address is idempotent
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output logic SelTIM, // Select a tightly integrated memory
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// Faults
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output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,
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output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
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output logic DAPageFault,
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output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
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output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources
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output logic DAPageFault, // page fault due to setting dirty or access bit
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output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources
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// PMA checker signals
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses
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);
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logic [`PA_BITS-1:0] TLBPAdr;
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// Translation lookaside buffer
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logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
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logic PMALoadAccessFaultM, PMPLoadAccessFaultM;
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logic PMAStoreAmoAccessFaultM, PMPStoreAmoAccessFaultM;
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logic DataMisalignedM;
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logic Translate;
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logic TLBHit;
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logic TLBPageFault;
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logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB
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logic PMAInstrAccessFaultF; // Instruction access fault from PMA
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logic PMPInstrAccessFaultF; // Instruction access fault from PMP
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logic PMALoadAccessFaultM; // Load access fault from PMA
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logic PMPLoadAccessFaultM; // Load access fault from PMP
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logic PMAStoreAmoAccessFaultM; // Store or AMO access fault from PMA
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logic PMPStoreAmoAccessFaultM; // Store or AMO access fault from PMP
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logic DataMisalignedM; // load or store misaligned
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logic Translate; // Translation occurs when virtual memory is active and DisableTranslation is off
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logic TLBHit; // Hit in TLB
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logic TLBPageFault; // Page fault from TLB
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// only instantiate TLB if Virtual Memory is supported
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if (`VIRTMEM_SUPPORTED) begin:tlb
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logic ReadAccess, WriteAccess;
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assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
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assign WriteAccess = WriteAccessM;
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tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU))
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tlb(.clk, .reset,
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tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
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.clk, .reset,
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.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
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.SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
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.VAdr(VAdr[`XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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@ -111,11 +91,9 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
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// If translation is occuring, select translated physical address from TLB
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// the lower 12 bits are the page offset. These are never changed from the orginal
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// non translated address.
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//mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
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mux2 #(`PA_BITS-12) addressmux(VAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
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assign PhysicalAddress[11:0] = VAdr[11:0];
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///////////////////////////////////////////
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// Check physical memory accesses
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///////////////////////////////////////////
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