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Fixed bug which caused stores to take an extra clock cycle.

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This commit is contained in:
Ross Thompson 2021-07-26 12:22:53 -05:00
parent 79ebc53977
commit 915d8136e5
1 changed files with 0 additions and 2 deletions
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2
wally-pipelined/src/cache/dcache.sv vendored
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@ -553,7 +553,6 @@ module dcache
DCacheStall = 1'b0; DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1; SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1; SetDirtyM = 1'b1;
DCacheStall = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(StallWtoDCache) begin
@ -922,7 +921,6 @@ module dcache
DCacheStall = 1'b0; DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1; SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1; SetDirtyM = 1'b1;
DCacheStall = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(StallWtoDCache) begin if(StallWtoDCache) begin