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Fixed up the bit widths on the page table walker for rv32.

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This commit is contained in:
Ross Thompson 2021-07-02 15:45:05 -05:00
parent 7b3716c281
commit 8e3149517a
1 changed files with 3 additions and 3 deletions
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6
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -59,7 +59,7 @@ module pagetablewalker
input logic HPTWStall, input logic HPTWStall,
// *** modify to send to LSU // *** modify to send to LSU
output logic [`XLEN-1:0] MMUPAdr, output logic [`XLEN-1:0] MMUPAdr, // this probalby should be `PA_BITS wide
output logic MMUTranslate, // *** rename to HPTWReq output logic MMUTranslate, // *** rename to HPTWReq
output logic HPTWRead, output logic HPTWRead,
@ -234,7 +234,7 @@ module pagetablewalker
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
DTLBWriteM = DTLBMissMQ; DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
end end
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
else if (ValidPTE && ~LeafPTE) begin else if (ValidPTE && ~LeafPTE) begin
@ -263,7 +263,7 @@ module pagetablewalker
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
DTLBWriteM = DTLBMissMQ; DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
end else begin end else begin
NextWalkerState = FAULT; NextWalkerState = FAULT;
end end