forked from Github_Repos/cvw
Fixed Issue #65 fmv sign selection. Sign needs to come from most significant bit of raw X source without doing NaN Box fixes first.
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@ -160,6 +160,7 @@ module fpu (
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logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
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logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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logic mvsgn; // sign bit for extending move
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//////////////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////
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// Decode Stage: fctrl decoder, read register file
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// Decode Stage: fctrl decoder, read register file
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@ -278,21 +279,25 @@ module fpu (
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mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
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assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
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// select the result that may be written to the integer register - to IEU
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// select the result that may be written to the integer register with fmv - to IEU
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if(`FPSIZES == 1)
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if(`FPSIZES == 1) begin
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assign mvsgn = XE[`FLEN-1];
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assign SgnExtXE = XE;
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assign SgnExtXE = XE;
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else if(`FPSIZES == 2)
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end else if(`FPSIZES == 2) begin
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mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
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mux2 #(1) sgnmux (XE[`LEN1-1], XE[`FLEN-1],FmtE, mvsgn);
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else if(`FPSIZES == 3 | `FPSIZES == 4)
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mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{mvsgn}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
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mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]},
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end else if(`FPSIZES == 3 | `FPSIZES == 4) begin
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{{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]},
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mux4 #(1) sgnmux (XE[`H_LEN-1], XE[`S_LEN-1], XE[`D_LEN-1], XE[`LLEN-1], FmtE, mvsgn);
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{{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]},
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mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{mvsgn}}, XE[`H_LEN-1:0]},
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{{`FLEN-`S_LEN{mvsgn}}, XE[`S_LEN-1:0]},
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{{`FLEN-`D_LEN{mvsgn}}, XE[`D_LEN-1:0]},
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XE, FmtE, SgnExtXE);
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XE, FmtE, SgnExtXE);
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end
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if (`FLEN>`XLEN)
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if (`FLEN>`XLEN)
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assign IntSrcXE = SgnExtXE[`XLEN-1:0];
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assign IntSrcXE = SgnExtXE[`XLEN-1:0];
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else
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else
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assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
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assign IntSrcXE = {{`XLEN-`FLEN{mvsgn}}, SgnExtXE};
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mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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// E/M pipe registers
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// E/M pipe registers
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