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Ross Thompson
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pipelined/src/ifu/oldgsharepredictor2.sv
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134
pipelined/src/ifu/oldgsharepredictor2.sv
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Gshare predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module oldgsharepredictor2
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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output logic [1:0] DirPredictionF,
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// update
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input logic [4:0] InstrClassE,
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input logic [4:0] BPInstrClassE,
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input logic [4:0] BPInstrClassD,
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input logic [4:0] BPInstrClassF,
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output logic DirPredictionWrongE,
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input logic PCSrcE
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);
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logic [`BPRED_SIZE+1:0] GHR, GHRNext;
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logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
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logic PHTUpdateEN;
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logic BPClassWrongNonCFI;
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logic BPClassWrongCFI;
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logic BPClassRightNonCFI;
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logic BPClassRightBPWrong;
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logic BPClassRightBPRight;
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logic [1:0] DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionE;
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logic [6:0] GHRMuxSel;
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logic GHRUpdateEN;
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logic [`BPRED_SIZE-1:0] GHRLookup;
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assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
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assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
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assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
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// GHR update selection, 1 hot encoded.
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assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
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assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
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assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
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assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
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assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
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assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
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assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
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assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
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// hoping this created a AND-OR mux.
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always_comb begin
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case (GHRMuxSel)
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7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
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7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
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7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
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7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
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7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
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7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
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7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
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default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
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endcase
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end
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flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
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.reset(reset),
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.en((GHRUpdateEN)),
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.d(GHRNext),
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.q(GHR));
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// if actively updating the GHR at the time of prediction we want to us
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// GHRNext as the lookup rather than GHR.
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assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
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assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
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assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
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assign PHTUpdateEN = InstrClassE[0] & ~StallE;
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assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
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// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
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ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
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.reset(reset),
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//.RA1(GHR[`BPRED_SIZE-1:0]),
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.ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
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.rd1(DirPredictionF),
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.ren1(~StallF),
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.wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
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.wd2(NewDirPredictionE),
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.wen2(PHTUpdateEN),
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.bwe2(2'b11));
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
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endmodule // gsharePredictor
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