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Cache name clarifications.

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This commit is contained in:
Ross Thompson 2022-02-10 10:50:17 -06:00
parent 32eee5a06a
commit 88c7a94aa9
2 changed files with 17 additions and 20 deletions
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6
pipelined/src/cache/cache.sv vendored
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@ -118,10 +118,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.WriteWordWayEn, .WriteWordWayEn,
.WriteLineWayEn, .WriteLineWayEn,
.CacheWriteData, .CacheWriteData,
.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay), .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay,
.SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelEvict, .VictimWay, .FlushWay,
.SelFlush, .SelFlush,
.SelectedReadDataLine(ReadDataLineWay), .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay), .ReadDataLineWay, .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.InvalidateAll(InvalidateCacheM)); .InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(

31
pipelined/src/cache/cacheway.sv vendored
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@ -40,17 +40,17 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic WriteWordWayEn, input logic WriteWordWayEn,
input logic WriteLineWayEn, input logic WriteLineWayEn,
input logic [LINELEN-1:0] CacheWriteData, input logic [LINELEN-1:0] CacheWriteData,
input logic SetValid, input logic SetValidWay,
input logic ClearValid, input logic ClearValidWay,
input logic SetDirty, input logic SetDirtyWay,
input logic ClearDirty, input logic ClearDirtyWay,
input logic SelEvict, input logic SelEvict,
input logic Victim, input logic VictimWay,
input logic InvalidateAll, input logic InvalidateAll,
input logic SelFlush, input logic SelFlush,
input logic Flush, input logic FlushWay,
output logic [LINELEN-1:0] SelectedReadDataLine, output logic [LINELEN-1:0] ReadDataLineWay,
output logic WayHit, output logic WayHit,
output logic VictimDirty, output logic VictimDirty,
output logic [TAGLEN-1:0] VictimTag); output logic [TAGLEN-1:0] VictimTag);
@ -69,8 +69,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
logic SelTag; logic SelTag;
logic [$clog2(NUMLINES)-1:0] RAdrD; logic [$clog2(NUMLINES)-1:0] RAdrD;
logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD;
logic [2**LOGWPL-1:0] MemPAdrDecoded; logic [2**LOGWPL-1:0] MemPAdrDecoded;
logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn;
@ -93,7 +91,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn));
// AND portion of distributed tag multiplexer // AND portion of distributed tag multiplexer
assign SelTag = SelFlush ? Flush : Victim; assign SelTag = SelFlush ? FlushWay : VictimWay;
assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux
assign VictimDirty = SelTag & Dirty & Valid; assign VictimDirty = SelTag & Dirty & Valid;
@ -112,8 +110,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
// AND portion of distributed read multiplexers // AND portion of distributed read multiplexers
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
mux3 #(1) selecteddatamux(WayHit, Victim, Flush, {SelFlush, SelEvict}, SelData); mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux. assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Valid Bits // Valid Bits
@ -121,8 +119,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
always_ff @(posedge clk) begin // Valid bit array, always_ff @(posedge clk) begin // Valid bit array,
if (reset | InvalidateAll) ValidBits <= #1 '0; if (reset | InvalidateAll) ValidBits <= #1 '0;
else if (SetValid) ValidBits[RAdr] <= #1 1'b1; else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
else if (ClearValid) ValidBits[RAdr] <= #1 1'b0; else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
end end
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
assign Valid = ValidBits[RAdrD]; assign Valid = ValidBits[RAdrD];
@ -135,10 +133,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
if (DIRTY_BITS) begin:dirty if (DIRTY_BITS) begin:dirty
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
else if (SetDirty) DirtyBits[RAdr] <= #1 1'b1; else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1;
else if (ClearDirty) DirtyBits[RAdr] <= #1 1'b0; else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
end end
flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
assign Dirty = DirtyBits[RAdrD]; assign Dirty = DirtyBits[RAdrD];
end else assign Dirty = 1'b0; end else assign Dirty = 1'b0;