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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Ross Thompson 2023-03-27 10:22:48 -05:00
commit 88c572d9bb
21 changed files with 1454 additions and 110 deletions
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2
config/buildroot/wally-config.vh
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@ -29,7 +29,7 @@
`include "wally-shared.vh"
`define FPGA 1
`define QEMU 1
`define QEMU 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64

33
sim/imperas.ic
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@ -1,5 +1,7 @@
#--showoverrides
#--showcommands
#--mpdconsole
#--gdbconsole
--showoverrides
--showcommands
# Core settings
--override cpu/unaligned=F
@ -9,7 +11,12 @@
--override cpu/misa_Extensions_mask=0x0
# THIS NEEDS FIXING to 16
--override cpu/PMP_registers=0
--override cpu/PMP_registers=16
--override cpu/PMP_undefined=T
# Illegal instruction should not contain the bit pattern
# illegal pmp read contained this
# --override cpu/tval_ii_code=F
# PMA Settings
# 'r': read access allowed
@ -24,16 +31,16 @@
# '8': 8-byte accesses allowed
# '-', space: ignored (use for input string formatting).
#
# SV39 Memory 0x0000000000 0x7FFFFFFFFF
# SVxx Memory 0x0000000000 0x7FFFFFFFFF
#
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- "; # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 "; # BOOTROM
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 "; # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 "; # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- "; # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- "; # UART0 error - 0x10000000 - 0x100000FF
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- "; # GPIO error - 0x10006000 - 0x100060FF
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 "; # UNCORE_RAM
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10006000 - 0x100060FF
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
# Enable the Imperas instruction coverage
#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
@ -42,7 +49,7 @@
# Add Imperas simulator application instruction tracing
--override cpu/show_c_prefix=T
--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange
--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
# Exceptions and pagetables debug
--override cpu/debugflags=6

9
sim/run-imperas-linux.sh Executable file
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@ -0,0 +1,9 @@
#!/bin/bash
export RISCV=/scratch/moore/RISCV
export IMPERAS_TOOLS=$(pwd)/imperas.ic
export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"

2
sim/wally-imperas-cov.do
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@ -51,7 +51,7 @@ vlog +incdir+../config/$1 \
-suppress 7063 \
+acc
vopt +acc work.testbench -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7 \
eval vsim workopt +nowarn3829 -fatal 7 \
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \
-do "coverage save -onexit ./riscv.ucdb"

2
sim/wally-imperas-no-idv.do
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@ -34,7 +34,7 @@ vlog +incdir+../config/$1 \
-suppress 2583 \
-suppress 7063
vopt +acc work.testbench -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7 \
eval vsim workopt +nowarn3829 -fatal 7 \
+testDir=$env(TESTDIR) $env(OTHERFLAGS)
view wave
#-- display input and output signals as hexidecimal values

2
sim/wally-imperas.do
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@ -45,7 +45,7 @@ vlog +incdir+../config/$1 \
-suppress 7063
vopt +acc work.testbench -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7 \
eval vsim workopt +nowarn3829 -fatal 7 \
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+testDir=$env(TESTDIR) $env(OTHERFLAGS)
view wave

150
sim/wally-linux-imperas.do Normal file
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@ -0,0 +1,150 @@
# wally.do
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
#-- Run the Simulation
#run -all
add log -recursive /*
do linux-wave.do
run -all
exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "buildroot-no-trace"} {
vlog -lint -work work_${1}_${2} \
+define+USE_IMPERAS_DV \
+incdir+../config/$1 \
+incdir+../config/shared \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
../testbench/testbench-linux-imperas.sv \
../testbench/common/*.sv ../src/*/*.sv \
../src/*/*/*.sv -suppress 2583
#
# start and run simulation
# for profiling add
# vopt -fprofile
# vsim -fprofile+perf
# visualizer -fprofile+perf+dir=fprofile
#
eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
-G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
$env(OTHERFLAGS)
#-- Run the Simulation
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
echo "Don't forget to change DEBUG_LEVEL = 0."
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
#run 100 ns
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
run 14000 ms
#add log -recursive /*
#do linux-wave.do
#run -all
exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "fpga"} {
echo "hello"
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
vsim workopt +nowarn3829 -fatal 7
do fpga-wave.do
add log -r /*
run 20 ms
} else {
if {$2 eq "ahb"} {
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
} else {
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
}
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7
view wave
#-- display input and output signals as hexidecimal values
#do ./wave-dos/peripheral-waves.do
add log -recursive /*
do wave.do
#do wave-bus.do
# power add generates the logging necessary for saif generation.
#power add -r /dut/core/*
#-- Run the Simulation
run -all
#power off -r /dut/core/*
#power report -all -bsaif power.saif
noview ../testbench/testbench.sv
view wave
}
#elseif {$2 eq "buildroot-no-trace""} {
# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
#-- Run the Simulation
# run 100 ns
# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
# add log -recursive /*
# do linux-wave.do
# run -all
# exec ./slack-notifier/slack-notifier.py
#}

11
src/ieu/alu.sv
View File

@ -52,19 +52,12 @@ module alu #(parameter WIDTH=32) (
logic LT, LTU; // Less than, Less than unsigned
logic Asign, Bsign; // Sign bits of A, B
// *** explain this part better; possibly move into shifter and BMU?
if (WIDTH == 64) begin
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
end else begin
assign CondExtA = A;
end
// Addition
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts (configurable for rotation)
shifter sh(.A(CondExtA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
// Condition code flags are based on subtraction output Sum = A-B.
// Overflow occurs when the numbers being subtracted have the opposite sign
@ -97,7 +90,7 @@ module alu #(parameter WIDTH=32) (
// Final Result B instruction select mux
if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
.Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult,
.Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
.CondMaskB, .CondShiftA, .Result);
end else begin
assign Result = ALUResult;

7
src/ieu/bmu/bitmanipalu.sv
View File

@ -37,7 +37,6 @@ module bitmanipalu #(parameter WIDTH=32) (
input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
input logic [1:0] CompFlags, // Comparator flags
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal
input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
@ -50,6 +49,7 @@ module bitmanipalu #(parameter WIDTH=32) (
logic Mask; // Indicates if it is ZBS instruction
logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal
// Extract control signals from bitmanip ALUControl.
assign {Mask, PreShift} = BALUControl[1:0];
@ -62,8 +62,11 @@ module bitmanipalu #(parameter WIDTH=32) (
// 0-3 bit Pre-Shift Mux
if (`ZBA_SUPPORTED) begin: zbapreshift
if (WIDTH == 64) begin
mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA);
end else assign CondZextA = A;
assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
assign CondShiftA = CondExtA << (PreShiftAmt);
assign CondShiftA = CondZextA << (PreShiftAmt);
end else begin
assign PreShiftAmt = 2'b0;
assign CondShiftA = A;

59
src/ieu/shifter.sv
View File

@ -35,55 +35,54 @@ module shifter (
input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift
output logic [`XLEN-1:0] Y); // Shifted result
logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
logic [`LOG_XLEN-1:0] amttrunc, Offset; // Shift amount adjusted for RV64, right-shift amount
logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount
logic Sign; // Sign bit for sign extension
assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension
if (`ZBB_SUPPORTED) begin: rotfunnel
if (`XLEN==32) begin // rv32 with rotates
if (`XLEN==32) begin // rv32
if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
always_comb // funnel mux
case({Right, Rotate})
2'b00: z = {A[31:0], 31'b0};
2'b01: z = {A[31:0], A[31:1]};
2'b10: z = {{31{Sign}}, A[31:0]};
2'b11: z = {A[30:0], A};
2'b00: Z = {A[31:0], 31'b0};
2'b01: Z = {A[31:0], A[31:1]};
2'b10: Z = {{31{Sign}}, A[31:0]};
2'b11: Z = {A[30:0], A[31:0]};
endcase
assign amttrunc = Amt; // shift amount
end else begin // rv64 with rotates
end else begin: norotfunnel32 //rv32 shifter without rotates
always_comb // funnel mux
if (Right) Z = {{31{Sign}}, A[31:0]};
else Z = {A[31:0], 31'b0};
end
assign TruncAmt = Amt; // shift amount
end else begin // rv64
logic [`XLEN-1:0] A64;
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
// shifter rotate source select mux
logic [`XLEN-1:0] RotA; // rotate source
mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
always_comb // funnel mux
case ({Right, Rotate})
2'b00: z = {A[63:0],{63'b0}};
2'b01: z = {RotA, RotA[63:1]};
2'b10: z = {{63{Sign}}, A[63:0]};
2'b11: z = {RotA[62:0], RotA};
2'b00: Z = {A64[63:0],{63'b0}};
2'b01: Z = {RotA[63:0], RotA[63:1]};
2'b10: Z = {{63{Sign}}, A64[63:0]};
2'b11: Z = {RotA[62:0], RotA[63:0]};
endcase
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
end else begin: norotfunnel
if (`XLEN==32) begin:shifter // RV32
end else begin: norotfunnel64 // rv64 shifter without rotates
always_comb // funnel mux
if (Right) z = {{31{Sign}}, A[31:0]};
else z = {A[31:0], 31'b0};
assign amttrunc = Amt; // shift amount
end else begin:shifter // RV64
always_comb // funnel mux
if (Right) z = {{63{Sign}}, A[63:0]};
else z = {A[63:0], {63'b0}};
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
if (Right) Z = {{63{Sign}}, A64[63:0]};
else Z = {A64[63:0], {63'b0}};
end
assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
// Opposite offset for right shifts
assign Offset = Right ? amttrunc : ~amttrunc;
assign Offset = Right ? TruncAmt : ~TruncAmt;
// Funnel operation
assign zshift = z >> Offset;
assign Y = zshift[`XLEN-1:0];
assign ZShift = Z >> Offset;
assign Y = ZShift[`XLEN-1:0];
endmodule

2
src/privileged/csrsr.sv
View File

@ -53,6 +53,8 @@ module csrsr (
logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE;
logic nextMBE, nextSBE;
initial $monitor("QEMU=%0d STATUS_SXL=%0d STATUS_UXL=%0d", `QEMU, STATUS_SXL, STATUS_UXL);
// STATUS REGISTER FIELD
// See Privileged Spec Section 3.1.6
// Lower privilege status registers are a subset of the full status register

195
testbench/common/wallyTracer.sv
View File

@ -90,6 +90,7 @@ module wallyTracer(rvviTrace rvvi);
assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
logic valid;
int csrid;
always_comb begin
// Since we are detected the CSR change by comparing the old value we need to
@ -116,7 +117,6 @@ module wallyTracer(rvviTrace rvvi);
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
csrid = 12'h3A0 + i4;
//if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp);
CSRArray[csrid] = pmp;
end
@ -125,7 +125,6 @@ module wallyTracer(rvviTrace rvvi);
pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
csrid = 12'h3B0 + i;
//if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp);
CSRArray[csrid] = pmp;
end
@ -167,7 +166,17 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
end else begin // hold the old value if the pipeline is stalled.
// PMP CFG 3A0 to 3AF
for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid];
// PMP ADDR 3B0 to 3EF
for(csrid='h3B0; csrid<='h3EF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid];
CSRArray[12'h300] = CSRArrayOld[12'h300];
CSRArray[12'h310] = CSRArrayOld[12'h310];
CSRArray[12'h305] = CSRArrayOld[12'h305];
@ -209,7 +218,7 @@ module wallyTracer(rvviTrace rvvi);
end
end
genvar index;
genvar index;
assign rf[0] = '0;
for(index = 1; index < NUMREGS; index += 1)
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
@ -286,26 +295,176 @@ module wallyTracer(rvviTrace rvvi);
// record previous csr value.
integer index4;
always_ff @(posedge clk) begin
for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin
// IMPERAS
//CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0;
CSRArrayOld[index4] = CSRArray[index4];
end
CSRArrayOld[12'h300] = CSRArray[12'h300];
CSRArrayOld[12'h310] = CSRArray[12'h310];
CSRArrayOld[12'h305] = CSRArray[12'h305];
CSRArrayOld[12'h341] = CSRArray[12'h341];
CSRArrayOld[12'h306] = CSRArray[12'h306];
CSRArrayOld[12'h320] = CSRArray[12'h320];
CSRArrayOld[12'h302] = CSRArray[12'h302];
CSRArrayOld[12'h303] = CSRArray[12'h303];
CSRArrayOld[12'h344] = CSRArray[12'h344];
CSRArrayOld[12'h304] = CSRArray[12'h304];
CSRArrayOld[12'h301] = CSRArray[12'h301];
CSRArrayOld[12'hF14] = CSRArray[12'hF14];
CSRArrayOld[12'h340] = CSRArray[12'h340];
CSRArrayOld[12'h342] = CSRArray[12'h342];
CSRArrayOld[12'h343] = CSRArray[12'h343];
CSRArrayOld[12'hF11] = CSRArray[12'hF11];
CSRArrayOld[12'hF12] = CSRArray[12'hF12];
CSRArrayOld[12'hF13] = CSRArray[12'hF13];
CSRArrayOld[12'hF15] = CSRArray[12'hF15];
CSRArrayOld[12'h34A] = CSRArray[12'h34A];
// MCYCLE and MINSTRET
CSRArrayOld[12'hB00] = CSRArray[12'hB00];
CSRArrayOld[12'hB02] = CSRArray[12'hB02];
// supervisor CSRs
CSRArrayOld[12'h100] = CSRArray[12'h100];
CSRArrayOld[12'h104] = CSRArray[12'h104];
CSRArrayOld[12'h105] = CSRArray[12'h105];
CSRArrayOld[12'h141] = CSRArray[12'h141];
CSRArrayOld[12'h106] = CSRArray[12'h106];
CSRArrayOld[12'h180] = CSRArray[12'h180];
CSRArrayOld[12'h140] = CSRArray[12'h140];
CSRArrayOld[12'h143] = CSRArray[12'h143];
CSRArrayOld[12'h142] = CSRArray[12'h142];
CSRArrayOld[12'h144] = CSRArray[12'h144];
// user CSRs
CSRArrayOld[12'h001] = CSRArray[12'h001];
CSRArrayOld[12'h002] = CSRArray[12'h002];
CSRArrayOld[12'h003] = CSRArray[12'h003];
// PMP CFG 3A0 to 3AF
for(index4='h3A0; index4<='h3AF; index4++)
CSRArrayOld[index4] = CSRArray[index4];
// PMP ADDR 3B0 to 3EF
for(index4='h3B0; index4<='h3EF; index4++)
CSRArrayOld[index4] = CSRArray[index4];
end
// check for csr value change.
genvar index5;
for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin
// CSR_W should only indicate the change when the Writeback stage is not stalled and valid.
assign #2 CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0;
assign rvvi.csr_wb[0][0][index5] = CSR_W[index5];
assign rvvi.csr[0][0][index5] = CSRArray[index5];
assign #2 CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0;
assign #2 CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
assign #2 CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
assign #2 CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0;
assign #2 CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
assign #2 CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
assign #2 CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0;
assign #2 CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0;
assign #2 CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0;
assign #2 CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
assign #2 CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
assign #2 CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
assign #2 CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
assign #2 CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0;
assign #2 CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
assign #2 CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
assign #2 CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0;
assign #2 CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0;
assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300];
assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302];
assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342];
assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343];
assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
assign rvvi.csr_wb[0][0][12'h34A] = CSR_W[12'h34A];
assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100];
assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104];
assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300];
assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305];
assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341];
assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306];
assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320];
assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302];
assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342];
assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343];
assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11];
assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12];
assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13];
assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15];
assign rvvi.csr[0][0][12'h34A] = CSRArray[12'h34A];
assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00];
assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02];
assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100];
assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104];
assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
// PMP CFG 3A0 to 3AF
for(index='h3A0; index<='h3AF; index++) begin
assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
assign rvvi.csr[0][0][index] = CSRArray[index];
end
// always @rvvi.clk $display("%t @rvvi.clk=%X", $time, rvvi.clk);
// always @rvvi.csr[0][0]['h300] $display("%t rvvi.csr[0][0]['h300]=%X", $time, rvvi.csr[0][0]['h300]);
// always @rvvi.csr_wb[0][0]['h300] $display("%t rvvi.csr_wb[0][0]['h300]=%X", $time, rvvi.csr_wb[0][0]['h300]);
// always @rvvi.valid[0][0] $display("%t rvvi.valid[0][0]=%X", $time, rvvi.valid[0][0]);
// PMP ADDR 3B0 to 3EF
for(index='h3B0; index<='h3EF; index++) begin
assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
assign rvvi.csr[0][0][index] = CSRArray[index];
end
// *** implementation only cancel? so sc does not clear?
assign rvvi.lrsc_cancel[0][0] = '0;

1030
testbench/testbench-linux-imperas.sv Normal file
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File diff suppressed because it is too large Load Diff

21
testbench/tests.vh
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@ -1852,7 +1852,6 @@ string arch64zbs[] = '{
string wally64priv[] = '{
`WALLYTEST,
// "rv64i_m/privilege/src/BUG66",
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
"rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
"rv64i_m/privilege/src/WALLY-mie-01.S",
@ -1863,15 +1862,15 @@ string arch64zbs[] = '{
"rv64i_m/privilege/src/WALLY-mtvec-01.S",
"rv64i_m/privilege/src/WALLY-pma-01.S",
"rv64i_m/privilege/src/WALLY-pmp-01.S",
// "rv64i_m/privilege/src/WALLY-sie-01.S",
"rv64i_m/privilege/src/WALLY-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-mie-01.S",
// "rv64i_m/privilege/src/WALLY-status-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-sie-01.S",
"rv64i_m/privilege/src/WALLY-status-tw-01.S",
"rv64i_m/privilege/src/WALLY-status-tvm-01.S",
"rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S",
// "rv64i_m/privilege/src/WALLY-stvec-01.S",
// "rv64i_m/privilege/src/WALLY-trap-01.S",
// "rv64i_m/privilege/src/WALLY-trap-s-01.S",
"rv64i_m/privilege/src/WALLY-stvec-01.S",
"rv64i_m/privilege/src/WALLY-trap-01.S",
"rv64i_m/privilege/src/WALLY-trap-s-01.S",
"rv64i_m/privilege/src/WALLY-trap-sret-01.S",
"rv64i_m/privilege/src/WALLY-trap-u-01.S",
"rv64i_m/privilege/src/WALLY-wfi-01.S",
@ -1951,15 +1950,15 @@ string arch64zbs[] = '{
"rv32i_m/privilege/src/WALLY-mtvec-01.S",
"rv32i_m/privilege/src/WALLY-pma-01.S",
"rv32i_m/privilege/src/WALLY-pmp-01.S",
// "rv32i_m/privilege/src/WALLY-sie-01.S",
"rv32i_m/privilege/src/WALLY-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-mie-01.S",
// "rv32i_m/privilege/src/WALLY-status-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-sie-01.S",
"rv32i_m/privilege/src/WALLY-status-tw-01.S",
"rv32i_m/privilege/src/WALLY-status-tvm-01.S",
"rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S",
// "rv32i_m/privilege/src/WALLY-stvec-01.S",
// "rv32i_m/privilege/src/WALLY-trap-01.S",
// "rv32i_m/privilege/src/WALLY-trap-s-01.S",
"rv32i_m/privilege/src/WALLY-stvec-01.S",
"rv32i_m/privilege/src/WALLY-trap-01.S",
"rv32i_m/privilege/src/WALLY-trap-s-01.S",
"rv32i_m/privilege/src/WALLY-trap-sret-01.S",
"rv32i_m/privilege/src/WALLY-trap-u-01.S",
"rv32i_m/privilege/src/WALLY-wfi-01.S",

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -29,10 +29,6 @@
00000008 # scause from U mode ecall
00000000 # stval of ecall (*** defined to be zero for now)
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec01 # value to indicate successful vectoring on s soft interrupt
80000001 # scause value from s soft interrupt
00000000 # stval for ssoft interrupt (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt
80000003 # scause value from m soft interrupt
00000000 # stval for msoft interrupt (0x0)

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
//jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -60,14 +60,6 @@
00000000
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec01 # value to indicate successful vectoring on s soft interrupt
00000000
00000001 # scause value from s soft interrupt
80000000
00000000 # stval for ssoft interrupt (0x0)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000
00000003 # scause value from m soft interrupt

5
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -162,6 +162,11 @@ cause_s_soft_interrupt:
csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_s_soft_from_m_interrupt:
li t3, 0x2
csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_m_ext_interrupt:
// ========== Configure PLIC ==========
li a3, 0x40

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
View File

@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes
GOTO_M_MODE
jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
GOTO_U_MODE // Should cause software interrupt to fire off.

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -50,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall
jal cause_s_soft_interrupt
jal cause_s_soft_from_m_interrupt
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
@ -72,7 +72,7 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall // M mode ecall
jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
//jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt