gave integer bits to D instead of adding manually everywhere

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -57,7 +57,7 @@ module fdivsqrt(
 
   logic [`DIVb+3:0]           WS, WC;                       // Partial remainder components
   logic [`DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [`DIVb-1:0]           D;                  // Iterator Divisor
+  logic [`DIVb+3:0]           D;                  // Iterator Divisor
   logic [`DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [`DIVb+1:0]           FirstC;                       // Step tracker
   logic                       Firstun;                      // Quotient selection

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -33,8 +33,7 @@ module fdivsqrtiter(
   input  logic             IFDivStartE, 
   input  logic             FDivBusyE, 
   input  logic             SqrtE,
-  input  logic [`DIVb+3:0] X,
+  input  logic [`DIVb+3:0] X, D,
-  input  logic [`DIVb-1:0] D,
   output logic [`DIVb:0]   FirstU, FirstUM,
   output logic [`DIVb+1:0] FirstC,
   output logic             Firstun,
@@ -95,12 +94,10 @@ module fdivsqrtiter(
   flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
 
   // Divisor Selections
-  //  - choose the negitive version of what's being selected
+  assign DBar    = ~D;        // for -D
-  //  - D is a 0.b mantissa
-  assign DBar    = {3'b111, 1'b0, ~D};
   if(`RADIX == 4) begin : d2
-    assign DBar2 = {2'b11, 1'b0, ~D, 1'b1};
+    assign D2    = D << 1;    // for 2D,  only used in R4
-    assign D2    = {2'b0, 1'b1, D, 1'b0};
+    assign DBar2 = ~D2;       // for -2D, only used in R4
   end
 
   // k=DIVCOPIES of the recurrence logic

src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -32,7 +32,7 @@ module fdivsqrtpostproc(
   input  logic              clk, reset,
   input  logic              StallM,
   input  logic [`DIVb+3:0]  WS, WC,
-  input  logic [`DIVb-1:0]  D, 
+  input  logic [`DIVb+3:0]  D, 
   input  logic [`DIVb:0]    FirstU, FirstUM, 
   input  logic [`DIVb+1:0]  FirstC,
   input  logic              SqrtE,
@@ -46,7 +46,7 @@ module fdivsqrtpostproc(
   output logic [`XLEN-1:0]  FIntDivResultM
 );
   
-  logic [`DIVb+3:0]         W, Sum, DM;
+  logic [`DIVb+3:0]         W, Sum;
   logic [`DIVb:0]           PreQmM;
   logic                     NegStickyM;
   logic                     weq0E, WZeroM;
@@ -67,7 +67,7 @@ module fdivsqrtpostproc(
 
     assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
     assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
-    assign FZeroDivE =  {3'b001,D,1'b0};                                    // F for divide
+    assign FZeroDivE =  D << 1;                                    // F for divide
     mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
@@ -102,11 +102,10 @@ module fdivsqrtpostproc(
     logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
 
     assign W = $signed(Sum) >>> `LOGR;
-    assign DM = {4'b0001, D};
     assign UnsignedQuotM = {3'b000, PreQmM};
 
     // Integer remainder: sticky and sign correction muxes
-    mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
+    mux2 #(`DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
     mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
     mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
 

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -38,8 +38,7 @@ module fdivsqrtpreproc (
   input  logic                XZeroE,
   input  logic [2:0]          Funct3E,
   output logic [`NE+1:0]      QeM,
-  output logic [`DIVb+3:0]    X,
+  output logic [`DIVb+3:0]    X, D,
-  output logic [`DIVb-1:0]    D,
   // Int-specific
   input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic                IntDivE, W64E,
@@ -111,7 +110,9 @@ module fdivsqrtpreproc (
   // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
   mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
   assign DivX = {3'b000, ~NumerZeroE, XPreproc};
-  // *** CT 4/13/23 Create D output here with leading 1 appended as well, use in the other modules
+
+   // Divisior register
+  flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
 
   // ***CT: factor out fdivsqrtcycles
   if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
@@ -173,8 +174,5 @@ module fdivsqrtpreproc (
   // Floating-point exponent
   fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
   flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
-
-   // Divisior register
-  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
 endmodule
 

src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -30,8 +30,7 @@
 
 /* verilator lint_off UNOPTFLAT */
 module fdivsqrtstage2 (
-  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0] D, DBar, 
-  input  logic [`DIVb+3:0] DBar, 
   input  logic [`DIVb:0]   U, UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
@@ -66,7 +65,7 @@ module fdivsqrtstage2 (
   always_comb
     if      (up) Dsel = DBar;
     else if (uz) Dsel = '0;
-    else         Dsel = {4'b0001, D}; // un
+    else         Dsel = D; // un
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD

src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -29,8 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtstage4 (
-  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0] D, DBar, D2, DBar2,
-  input  logic [`DIVb+3:0] DBar, D2, DBar2,
   input  logic [`DIVb:0]   U,UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
@@ -75,7 +74,7 @@ module fdivsqrtstage4 (
       4'b1000: Dsel = DBar2;
       4'b0100: Dsel = DBar;
       4'b0000: Dsel = '0;
-      4'b0010: Dsel = {3'b0, 1'b1, D};
+      4'b0010: Dsel = D;
       4'b0001: Dsel = D2;
       default: Dsel = 'x;
     endcase