forked from Github_Repos/cvw
FPGA makefile update.
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@ -3,9 +3,9 @@ sdc_src := ~/repos/sdc.tar.gz
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# Select the desired board and the all build rules
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# vcu118
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#export XILINX_PART := xcvu9p-flga2104-2L-e
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#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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#export board := vcu118
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export XILINX_PART := xcvu9p-flga2104-2L-e
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export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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export board := vcu118
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# vcu108
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#export XILINX_PART := xcvu095-ffva2104-2-e
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@ -13,15 +13,15 @@ sdc_src := ~/repos/sdc.tar.gz
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#export board := vcu108
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# Arty A7
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export XILINX_PART := xc7a100tcsg324-1
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export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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export board := ArtyA7
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#export XILINX_PART := xc7a100tcsg324-1
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#export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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#export board := ArtyA7
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# for Arty A7 and S7 boards
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all: FPGA_Arty
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#all: FPGA_Arty
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# VCU 108 and VCU 118 boards
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#all: FPGA_VCU
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all: FPGA_VCU
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FPGA_Arty: PreProcessFiles IP_Arty SDC
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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