forked from Github_Repos/cvw
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
This commit is contained in:
Ross Thompson
parent
d15cb64bdf
commit
862bf2faae
@ -274,11 +274,11 @@ connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/core/priv.p
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe64]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
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connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAccessFaultM ]]
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connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe65]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
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connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreMisalignedFaultM ]]
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connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe66]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
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@ -20,9 +20,9 @@ add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadPageFaultM
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@ -403,7 +403,7 @@ add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/
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add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PhysicalAddress
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/TLBPageFault
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/LoadAccessFaultM
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/StoreAccessFaultM
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/StoreAmoAccessFaultM
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add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/TLBPAdr
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add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/PTE
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add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/TLBWrite
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@ -415,10 +415,10 @@ add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/l
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add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/pmachecker/PMAAccessFault
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add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAInstrAccessFaultF
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add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMALoadAccessFaultM
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add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAStoreAccessFaultM
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add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAStoreAmoAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPStoreAmoAccessFaultM
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add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/wallypipelinedsoc/core/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/PCF
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/genblk1/TranslationVAdr
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@ -20,14 +20,14 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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@ -333,7 +333,7 @@ add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/d
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAccessFaultM
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
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add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
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add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
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@ -345,7 +345,7 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAccessFaultM
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
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@ -353,7 +353,7 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dm
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
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@ -159,8 +159,8 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalBaseInstrFaultD
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add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalIEUInstrFaultD
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add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrMisalignedAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/zero
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add wave -noupdate -radix hexadecimal /testbench/dut/core/PCSrcE
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@ -649,8 +649,8 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataW
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clk
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/reset
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add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear
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@ -733,8 +733,8 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultF
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultD
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TimerIntM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ExtIntM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SwIntM
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@ -1252,9 +1252,9 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrAccessF
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/IllegalInstrFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/BreakpointFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/EcallFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrPageFaultM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadPageFaultM
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@ -20,9 +20,9 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadPageFaultM
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@ -358,7 +358,7 @@ add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/TLBHit
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add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/PhysicalAddress
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/TLBPageFault
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/LoadAccessFaultM
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/StoreAccessFaultM
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add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/StoreAmoAccessFaultM
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add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBPAdr
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add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/PTE
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add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBWrite
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@ -370,10 +370,10 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/AtomicAllo
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add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/PMAAccessFault
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add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAInstrAccessFaultF
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add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMALoadAccessFaultM
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add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAStoreAccessFaultM
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add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAStoreAmoAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPStoreAmoAccessFaultM
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add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/PCF
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
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@ -19,9 +19,9 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
@ -327,7 +327,7 @@ add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBH
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
@ -340,7 +340,7 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Atomi
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
@ -348,7 +348,7 @@ add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpch
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
|
||||
Binary file not shown.
@ -62,7 +62,7 @@ module ifu (
|
||||
output logic BPPredClassNonCFIWrongM,
|
||||
// Faults
|
||||
input logic IllegalBaseInstrFaultD,
|
||||
output logic ITLBInstrPageFaultF,
|
||||
output logic InstrPageFaultF,
|
||||
output logic IllegalIEUInstrFaultD,
|
||||
output logic InstrMisalignedFaultM,
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM,
|
||||
@ -190,13 +190,15 @@ module ifu (
|
||||
.TLBFlush(ITLBFlushF),
|
||||
.PhysicalAddress(PCPF),
|
||||
.TLBMiss(ITLBMissF),
|
||||
.TLBPageFault(ITLBInstrPageFaultF),
|
||||
.InstrPageFaultF,
|
||||
.ExecuteAccessF(1'b1),
|
||||
.AtomicAccessM(1'b0),
|
||||
.ReadAccessM(1'b0),
|
||||
.WriteAccessM(1'b0),
|
||||
.LoadAccessFaultM(),
|
||||
.StoreAccessFaultM(),
|
||||
.StoreAmoAccessFaultM(),
|
||||
.LoadPageFaultM(), .StoreAmoPageFaultM(),
|
||||
.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
|
||||
.DisableTranslation(1'b0), // *** is there a better name
|
||||
.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
|
||||
|
||||
|
||||
@ -56,10 +56,10 @@ module lsu (
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic DTLBFlushM,
|
||||
// faults
|
||||
output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
|
||||
output logic LoadPageFaultM, StoreAmoPageFaultM,
|
||||
output logic LoadMisalignedFaultM, LoadAccessFaultM,
|
||||
// cpu hazard unit (trap)
|
||||
output logic StoreMisalignedFaultM, StoreAccessFaultM,
|
||||
output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
|
||||
// connect to ahb
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr,
|
||||
(* mark_debug = "true" *) output logic LSUBusRead,
|
||||
@ -81,7 +81,6 @@ module lsu (
|
||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
|
||||
);
|
||||
|
||||
logic DTLBPageFaultM;
|
||||
logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache
|
||||
logic [`XLEN+1:0] IEUAdrExtM;
|
||||
logic DTLBMissM;
|
||||
@ -169,7 +168,6 @@ module lsu (
|
||||
|
||||
// MMU and Misalignment fault logic required if privileged unit exists
|
||||
if(`ZICSR_SUPPORTED == 1) begin : dmmu
|
||||
logic DataMisalignedM;
|
||||
|
||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
@ -185,39 +183,27 @@ module lsu (
|
||||
.TLBMiss(DTLBMissM),
|
||||
.Cacheable(CacheableM),
|
||||
.Idempotent(), .AtomicAllowed(),
|
||||
.TLBPageFault(DTLBPageFaultM),
|
||||
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
|
||||
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
|
||||
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
|
||||
.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), // **** change this to just use PreLSURWM
|
||||
.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
|
||||
);
|
||||
|
||||
// *** lsumisaligned lsumisaligned(Funct3M, IEUAdrM, MemRW, LoadMisalignedFaultM, StoreMisalignedFaultM);
|
||||
// *** lsumisaligned lsumisaligned(Funct3M, IEUAdrM, MemRW, LoadMisalignedFaultM, StoreAmoMisalignedFaultM);
|
||||
// *** lump into lsumislaigned module
|
||||
// Determine if an Unaligned access is taking place
|
||||
// hptw guarantees alignment, only check inputs from IEU.
|
||||
|
||||
// *** modify MMU to put out LoadMisalignedFault and StoreMisalignedFault rather than DataMisalignedM
|
||||
always_comb
|
||||
case(Funct3M[1:0])
|
||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
|
||||
// If the CPU's (not HPTW's) request is a page fault.
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
|
||||
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
|
||||
// Specify which type of page fault is occurring
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLSURWM[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & PreLSURWM[0];
|
||||
|
||||
end else begin
|
||||
assign {DTLBMissM, DTLBPageFaultM, LoadAccessFaultM, StoreAccessFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM} = '0;
|
||||
assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
|
||||
assign LSUPAdrM = PreLSUPAdrM;
|
||||
assign CacheableM = 1;
|
||||
assign {DTLBLoadPageFaultM, DTLBStorePageFaultM} = '0;
|
||||
assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
|
||||
end
|
||||
assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
|
||||
|
||||
|
||||
@ -75,8 +75,9 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
|
||||
output logic Cacheable, Idempotent, AtomicAllowed,
|
||||
|
||||
// Faults
|
||||
output logic TLBPageFault,
|
||||
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAccessFaultM,
|
||||
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,
|
||||
output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
|
||||
output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
|
||||
|
||||
// PMA checker signals
|
||||
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
|
||||
@ -89,10 +90,11 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
|
||||
|
||||
logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
|
||||
logic PMALoadAccessFaultM, PMPLoadAccessFaultM;
|
||||
logic PMAStoreAccessFaultM, PMPStoreAccessFaultM;
|
||||
logic PMAStoreAmoAccessFaultM, PMPStoreAmoAccessFaultM;
|
||||
logic DataMisalignedM;
|
||||
logic Translate;
|
||||
logic TLBHit;
|
||||
|
||||
logic TLBPageFault;
|
||||
|
||||
// only instantiate TLB if Virtual Memory is supported
|
||||
if (`MEM_VIRTMEM) begin:tlb
|
||||
@ -130,17 +132,35 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
|
||||
pmachecker pmachecker(.PhysicalAddress, .Size,
|
||||
.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.Cacheable, .Idempotent, .AtomicAllowed,
|
||||
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAccessFaultM);
|
||||
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
|
||||
|
||||
pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAccessFaultM);
|
||||
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
|
||||
|
||||
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
|
||||
// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
|
||||
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
|
||||
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
|
||||
always_comb
|
||||
case(Size[1:0])
|
||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
|
||||
// If the CPU's (not HPTW's) request is a page fault.
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & ReadAccessM;
|
||||
assign StoreAmoMisalignedFaultM = DataMisalignedM & (WriteAccessM | AtomicAccessM);
|
||||
// Specify which type of page fault is occurring
|
||||
assign InstrPageFaultF = TLBPageFault & ExecuteAccessF;
|
||||
|
||||
assign LoadPageFaultM = TLBPageFault & ReadAccessM;
|
||||
assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | AtomicAccessM);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -41,7 +41,7 @@ module pmachecker (
|
||||
output logic Cacheable, Idempotent, AtomicAllowed,
|
||||
output logic PMAInstrAccessFaultF,
|
||||
output logic PMALoadAccessFaultM,
|
||||
output logic PMAStoreAccessFaultM
|
||||
output logic PMAStoreAmoAccessFaultM
|
||||
);
|
||||
|
||||
logic PMAAccessFault;
|
||||
@ -66,6 +66,6 @@ module pmachecker (
|
||||
assign PMAAccessFault = SelRegions[8] & AccessRWX;
|
||||
assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
|
||||
assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
|
||||
assign PMAStoreAccessFaultM = WriteAccessM & PMAAccessFault;
|
||||
assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -49,7 +49,7 @@ module pmpchecker (
|
||||
input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
|
||||
output logic PMPInstrAccessFaultF,
|
||||
output logic PMPLoadAccessFaultM,
|
||||
output logic PMPStoreAccessFaultM
|
||||
output logic PMPStoreAmoAccessFaultM
|
||||
);
|
||||
|
||||
if (`PMP_ENTRIES > 0) begin: pmpchecker
|
||||
@ -75,11 +75,11 @@ module pmpchecker (
|
||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
|
||||
|
||||
assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|X;
|
||||
assign PMPStoreAccessFaultM = EnforcePMP & WriteAccessM & ~|W;
|
||||
assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|W;
|
||||
assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|R;
|
||||
end else begin: pmpchecker // no checker
|
||||
assign PMPInstrAccessFaultF = 0;
|
||||
assign PMPLoadAccessFaultM = 0;
|
||||
assign PMPStoreAccessFaultM = 0;
|
||||
assign PMPStoreAmoAccessFaultM = 0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -51,10 +51,10 @@ module privileged (
|
||||
input logic ICacheMiss,
|
||||
input logic ICacheAccess,
|
||||
input logic PrivilegedM,
|
||||
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
|
||||
input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
|
||||
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
|
||||
input logic LoadMisalignedFaultM,
|
||||
input logic StoreMisalignedFaultM,
|
||||
input logic StoreAmoMisalignedFaultM,
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||
@ -66,7 +66,7 @@ module privileged (
|
||||
|
||||
input logic InstrAccessFaultF,
|
||||
input logic LoadAccessFaultM,
|
||||
input logic StoreAccessFaultM,
|
||||
input logic StoreAmoAccessFaultM,
|
||||
|
||||
output logic ExceptionM,
|
||||
output logic PendingInterruptM,
|
||||
@ -93,8 +93,7 @@ module privileged (
|
||||
logic IllegalCSRAccessM;
|
||||
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
|
||||
logic IllegalFPUInstrM;
|
||||
logic LoadPageFaultM, StorePageFaultM;
|
||||
logic InstrPageFaultF, InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
|
||||
logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
|
||||
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
|
||||
logic IllegalInstrFaultM, TrappedSRETM;
|
||||
|
||||
@ -201,11 +200,6 @@ module privileged (
|
||||
// A page fault might occur because of insufficient privilege during a TLB
|
||||
// lookup or a improperly formatted page table during walking
|
||||
|
||||
// *** merge these at the lsu level.
|
||||
assign InstrPageFaultF = ITLBInstrPageFaultF;
|
||||
assign LoadPageFaultM = DTLBLoadPageFaultM;
|
||||
assign StorePageFaultM = DTLBStorePageFaultM;
|
||||
|
||||
// pipeline fault signals
|
||||
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
|
||||
{InstrPageFaultF, InstrAccessFaultF},
|
||||
@ -219,9 +213,9 @@ module privileged (
|
||||
// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
|
||||
trap trap(.clk, .reset,
|
||||
.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
|
||||
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||
.LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
|
||||
.LoadPageFaultM, .StorePageFaultM,
|
||||
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
|
||||
.LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.mretM, .sretM, .uretM,
|
||||
.PrivilegeModeW, .NextPrivilegeModeM,
|
||||
.MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
|
||||
|
||||
@ -35,9 +35,9 @@ module trap (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
|
||||
(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadPageFaultM, StorePageFaultM,
|
||||
(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM,
|
||||
(* mark_debug = "true" *) input logic mretM, sretM, uretM,
|
||||
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
|
||||
@ -86,10 +86,10 @@ module trap (
|
||||
// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
|
||||
// Traps are the union of exceptions and interrupts.
|
||||
assign Exception1M = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
|
||||
LoadMisalignedFaultM | StoreMisalignedFaultM |
|
||||
InstrPageFaultM | LoadPageFaultM | StorePageFaultM |
|
||||
LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
|
||||
InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
|
||||
BreakpointFaultM | EcallFaultM |
|
||||
LoadAccessFaultM | StoreAccessFaultM;
|
||||
LoadAccessFaultM | StoreAmoAccessFaultM;
|
||||
assign TrapM = Exception1M | InterruptM; // *** clean this up later DH
|
||||
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
|
||||
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
|
||||
@ -144,11 +144,11 @@ module trap (
|
||||
else if (BreakpointFaultM) CauseM = 3;
|
||||
else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8;
|
||||
else if (LoadMisalignedFaultM) CauseM = 4;
|
||||
else if (StoreMisalignedFaultM) CauseM = 6;
|
||||
else if (StoreAmoMisalignedFaultM) CauseM = 6;
|
||||
else if (LoadPageFaultM) CauseM = 13;
|
||||
else if (StorePageFaultM) CauseM = 15;
|
||||
else if (StoreAmoPageFaultM) CauseM = 15;
|
||||
else if (LoadAccessFaultM) CauseM = 5;
|
||||
else if (StoreAccessFaultM) CauseM = 7;
|
||||
else if (StoreAmoAccessFaultM) CauseM = 7;
|
||||
else CauseM = 0;
|
||||
|
||||
// MTVAL
|
||||
@ -163,11 +163,11 @@ module trap (
|
||||
always_comb
|
||||
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
|
||||
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
|
||||
else if (InstrPageFaultM) NextFaultMtvalM = PCM;
|
||||
else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StorePageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
|
||||
else NextFaultMtvalM = 0;
|
||||
endmodule
|
||||
|
||||
@ -79,9 +79,9 @@ module wallypipelinedcore (
|
||||
(* mark_debug = "true" *) logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreMisalignedFaultM, StoreAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
logic InvalidateICacheM, FlushDCacheM;
|
||||
logic PCSrcE;
|
||||
@ -189,7 +189,7 @@ module wallypipelinedcore (
|
||||
|
||||
// output logic
|
||||
// Faults
|
||||
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF,
|
||||
.IllegalBaseInstrFaultD, .InstrPageFaultF,
|
||||
.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
|
||||
.InstrMisalignedAdrM,
|
||||
|
||||
@ -270,12 +270,12 @@ module wallypipelinedcore (
|
||||
.STATUS_MPP, // from csr
|
||||
|
||||
.DTLBFlushM, // connects to privilege
|
||||
.DTLBLoadPageFaultM, // connects to privilege
|
||||
.DTLBStorePageFaultM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
.StoreAmoPageFaultM, // connects to privilege
|
||||
.LoadMisalignedFaultM, // connects to privilege
|
||||
.LoadAccessFaultM, // connects to privilege
|
||||
.StoreMisalignedFaultM, // connects to privilege
|
||||
.StoreAccessFaultM, // connects to privilege
|
||||
.StoreAmoMisalignedFaultM, // connects to privilege
|
||||
.StoreAmoAccessFaultM, // connects to privilege
|
||||
|
||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
|
||||
.LSUStallM); // change to LSUStallM
|
||||
@ -327,9 +327,9 @@ module wallypipelinedcore (
|
||||
.BPPredDirWrongM, .BTBPredPCWrongM,
|
||||
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
|
||||
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.MTIME_CLINT,
|
||||
.InstrMisalignedAdrM, .IEUAdrM,
|
||||
@ -337,7 +337,7 @@ module wallypipelinedcore (
|
||||
// Trap signals from pmp/pma in mmu
|
||||
// *** do these need to be split up into one for dmem and one for ifu?
|
||||
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
|
||||
.InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
|
||||
.InstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM,
|
||||
.ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
|
||||
.PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user