Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.

pipelined/src/privileged/csri.sv

@@ -95,21 +95,20 @@ module csri #(parameter
 //      else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
 
   // restricted views of registers
-  always_comb begin:regs
+  // Add MEIP read-only signal
-    // Add MEIP read-only signal
+  assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
-    IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
 
     // Machine Mode
-    MIP_REGW = IP_REGW;
+  assign MIP_REGW = IP_REGW;
-    MIE_REGW = IE_REGW;
+  assign MIE_REGW = IE_REGW;
 
-    // Supervisor mode
+  // Supervisor mode
-    if (`S_SUPPORTED) begin
+  if (`S_SUPPORTED) begin
-      SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
+    assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
-      SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
+    assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
-    end else begin
+  end else begin
-      SIP_REGW = 12'b0;
+    assign SIP_REGW = 12'b0;
-      SIE_REGW = 12'b0;
+    assign SIE_REGW = 12'b0;
-    end
   end
+
 endmodule