forked from Github_Repos/cvw
		
	Divider cleanup
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				@ -42,7 +42,6 @@ module intdivrestoring (
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  logic Div0E, Div0M;
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					  logic Div0E, Div0M;
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  logic DivInitE, SignXE, SignXM, SignDE, SignDM, NegWM, NegQM;
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					  logic DivInitE, SignXE, SignXM, SignDE, SignDM, NegWM, NegQM;
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  logic SignedDivideM;
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					  logic SignedDivideM;
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  // *** add pipe stages to everything
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  // save inputs on the negative edge of the execute clock.  
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					  // save inputs on the negative edge of the execute clock.  
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  // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
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					  // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
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@ -66,8 +65,6 @@ module intdivrestoring (
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  neg #(`XLEN) negx(XSavedE, XnE);
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					  neg #(`XLEN) negx(XSavedE, XnE);
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  mux2 #(`XLEN) xabsmux(XSavedE, XnE, SignedDivideE & SignXE, XInitE);  // need original X as remainder if doing divide by 0
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					  mux2 #(`XLEN) xabsmux(XSavedE, XnE, SignedDivideE & SignXE, XInitE);  // need original X as remainder if doing divide by 0
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   // Put suffixes on XInitE, init->DivInitE, Wn, XQn
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  // initialization multiplexers on first cycle of operation (one cycle after start is asserted)
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					  // initialization multiplexers on first cycle of operation (one cycle after start is asserted)
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  mux2 #(`XLEN) wmux(WM, {`XLEN{1'b0}}, DivInitE, WE);
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					  mux2 #(`XLEN) wmux(WM, {`XLEN{1'b0}}, DivInitE, WE);
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  mux2 #(`XLEN) xmux(XQM, XInitE, DivInitE, XQE);
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					  mux2 #(`XLEN) xmux(XQM, XInitE, DivInitE, XQE);
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@ -76,6 +73,7 @@ module intdivrestoring (
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  intdivrestoringstep step1(WE, XQE, DAbsBE, W1E, XQ1E);
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					  intdivrestoringstep step1(WE, XQE, DAbsBE, W1E, XQ1E);
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  intdivrestoringstep step2(W1E, XQ1E, DAbsBE, WNextE, XQNextE);
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					  intdivrestoringstep step2(W1E, XQ1E, DAbsBE, WNextE, XQNextE);
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					  // registers after division steps
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  flopen #(`XLEN) wreg(clk, BusyE, WNextE, WM); 
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					  flopen #(`XLEN) wreg(clk, BusyE, WNextE, WM); 
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  flopen #(`XLEN) xreg(clk, BusyE, XQNextE, XQM);
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					  flopen #(`XLEN) xreg(clk, BusyE, XQNextE, XQM);
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