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Cachefsm gate LRUWriteEn with ~FlushStage

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Alec Vercruysse 2023-04-12 13:32:36 -07:00
parent e303d99d5b
commit 800f0245f3
2 changed files with 3 additions and 2 deletions
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2
src/cache/cache.sv vendored
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@ -129,7 +129,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Select victim way for associative caches // Select victim way for associative caches
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
.clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
end else end else
assign VictimWay = 1'b1; // one hot. assign VictimWay = 1'b1; // one hot.

3
src/cache/cachefsm.sv vendored
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@ -224,8 +224,9 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
// write enables internal to cache // write enables internal to cache
assign SetValid = CurrState == STATE_WRITE_LINE; assign SetValid = CurrState == STATE_WRITE_LINE;
// coverage off -item e 1 -fecexprrow 8
assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
(CurrState == STATE_WRITE_LINE); (CurrState == STATE_WRITE_LINE) & ~FlushStage;
assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
endmodule // cachefsm endmodule // cachefsm