forked from Github_Repos/cvw
Fixed for the instruction spills.
This commit is contained in:
Ross Thompson
parent
532c8771ba
commit
7b3735fc25
@ -1,4 +1,5 @@
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onerror {resume}
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quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /testbench/dut/hart/ifu/icache/cachemem { &{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0] }} offset
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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@ -8,19 +9,19 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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@ -59,15 +60,15 @@ add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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@ -207,13 +208,17 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheMemReadData
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/genblk2/PCPreFinalF_q
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/ReadLine
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add wave -noupdate -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[1]} -radix hexadecimal} {{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[0]} -radix hexadecimal}} -subitemconfig {{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[1]} {-height 16 -radix hexadecimal} {/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[0]} {-height 16 -radix hexadecimal}} /testbench/dut/hart/ifu/icache/cachemem/ReadOffset
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add wave -noupdate -label {read offset} -radix unsigned -childformat {{(4) -radix unsigned} {(3) -radix unsigned} {(2) -radix unsigned} {(1) -radix unsigned} {(0) -radix unsigned}} -subitemconfig {{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0]} {-radix unsigned}} /testbench/dut/hart/ifu/icache/cachemem/offset
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
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add wave -noupdate /testbench/dut/hart/ifu/CompressedF
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {1598 ns} 0}
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WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {9098514 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 229
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configure wave -valuecolwidth 513
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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@ -226,4 +231,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {1559 ns} {1783 ns}
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WaveRestoreZoom {9098483 ns} {9098569 ns}
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28
wally-pipelined/src/cache/dmapped.sv
vendored
28
wally-pipelined/src/cache/dmapped.sv
vendored
@ -140,7 +140,7 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
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input logic [LINESIZE-1:0] WriteLine,
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input logic [`XLEN-1:0] WritePAdr,
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// Output the word, as well as if it is valid
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output logic [WORDSIZE-1:0] DataWord,
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output logic [31:0] DataWord, // *** was WORDSIZE-1
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output logic DataValid
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);
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@ -202,7 +202,31 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
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);
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// Pick the right bits coming out the read line
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assign DataWord = ReadLineTransformed[ReadOffset];
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//assign DataWord = ReadLineTransformed[ReadOffset];
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//logic [31:0] tempRD;
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always_comb begin
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case (OldReadPAdr[4:1])
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0: DataWord = ReadLine[31:0];
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1: DataWord = ReadLine[47:16];
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2: DataWord = ReadLine[63:32];
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3: DataWord = ReadLine[79:48];
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4: DataWord = ReadLine[95:64];
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5: DataWord = ReadLine[111:80];
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6: DataWord = ReadLine[127:96];
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7: DataWord = ReadLine[143:112];
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8: DataWord = ReadLine[159:128];
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9: DataWord = ReadLine[175:144];
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10: DataWord = ReadLine[191:160];
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11: DataWord = ReadLine[207:176];
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12: DataWord = ReadLine[223:192];
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13: DataWord = ReadLine[239:208];
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14: DataWord = ReadLine[255:224];
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15: DataWord = {16'b0, ReadLine[255:240]};
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endcase
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end
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genvar i;
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generate
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for (i=0; i < LINESIZE/WORDSIZE; i++) begin
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@ -103,12 +103,12 @@ module icachecontroller #(parameter LINESIZE = 256) (
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// Signals to/from cache memory
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// The read coming out of it
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input logic [`XLEN-1:0] ICacheMemReadData,
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input logic [31:0] ICacheMemReadData,
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input logic ICacheMemReadValid,
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// The address at which we want to search the cache memory
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output logic [`XLEN-1:12] ICacheMemReadUpperPAdr,
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output logic [11:0] ICacheMemReadLowerAdr,
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output logic ICacheReadEn,
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output logic ICacheReadEn,
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// Load data into the cache
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output logic ICacheMemWriteEnable,
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output logic [LINESIZE-1:0] ICacheMemWriteData,
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@ -565,30 +565,13 @@ module icachecontroller #(parameter LINESIZE = 256) (
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.q(SpillDataBlock0));
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// use the not quite final PC to do the final selection.
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generate
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if( `XLEN == 32) begin
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logic [1:1] PCPreFinalF_q;
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flopenr #(1) PCFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(PCPreFinalF[1]),
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.q(PCPreFinalF_q[1]));
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assign FinalInstrRawF = PCPreFinalF_q[1] ? {SpillDataBlock0, ICacheMemReadData[31:16]} : ICacheMemReadData;
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end else begin
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logic [2:1] PCPreFinalF_q;
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flopenr #(2) PCFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(PCPreFinalF[2:1]),
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.q(PCPreFinalF_q[2:1]));
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mux4 #(32) AlignmentMux(.d0(ICacheMemReadData[31:0]),
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.d1(ICacheMemReadData[47:16]),
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.d2(ICacheMemReadData[63:32]),
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.d3({SpillDataBlock0, ICacheMemReadData[63:48]}),
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.s(PCPreFinalF_q[2:1]),
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.y(FinalInstrRawF));
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end
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endgenerate
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logic [1:1] PCPreFinalF_q;
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flopenr #(1) PCFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(PCPreFinalF[1]),
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.q(PCPreFinalF_q[1]));
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assign FinalInstrRawF = PCPreFinalF_q[1] ? {ICacheMemReadData[31:16], SpillDataBlock0} : ICacheMemReadData;
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// There is a frustrating issue on the first access.
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// The cache will not contain any valid data but will contain x's on
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