Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed for the instruction spills.

Browse Source
This commit is contained in:
Ross Thompson 2021-04-21 16:47:05 -05:00
parent 532c8771ba
commit 7b3735fc25
3 changed files with 66 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
wally-pipelined/regression/wave.do
View File

@ -1,4 +1,5 @@
onerror {resume} onerror {resume}
quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /testbench/dut/hart/ifu/icache/cachemem { &{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0] }} offset
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset
@ -8,19 +9,19 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
@ -59,15 +60,15 @@ add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
@ -207,13 +208,17 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPF
add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPFinalF add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPFinalF
add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheMemReadData add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheMemReadData
add wave -noupdate /testbench/dut/hart/ifu/icache/controller/genblk2/PCPreFinalF_q
add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/ReadLine
add wave -noupdate -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[1]} -radix hexadecimal} {{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[0]} -radix hexadecimal}} -subitemconfig {{/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[1]} {-height 16 -radix hexadecimal} {/testbench/dut/hart/ifu/icache/cachemem/ReadOffset[0]} {-height 16 -radix hexadecimal}} /testbench/dut/hart/ifu/icache/cachemem/ReadOffset
add wave -noupdate -label {read offset} -radix unsigned -childformat {{(4) -radix unsigned} {(3) -radix unsigned} {(2) -radix unsigned} {(1) -radix unsigned} {(0) -radix unsigned}} -subitemconfig {{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0]} {-radix unsigned}} /testbench/dut/hart/ifu/icache/cachemem/offset
add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
add wave -noupdate /testbench/dut/hart/ifu/CompressedF
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {1598 ns} 0} WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {9098514 ns} 0}
quietly wave cursor active 2 quietly wave cursor active 2
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 229 configure wave -valuecolwidth 513
configure wave -justifyvalue left configure wave -justifyvalue left
configure wave -signalnamewidth 1 configure wave -signalnamewidth 1
configure wave -snapdistance 10 configure wave -snapdistance 10
@ -226,4 +231,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {1559 ns} {1783 ns} WaveRestoreZoom {9098483 ns} {9098569 ns}

28
wally-pipelined/src/cache/dmapped.sv vendored
View File

@ -140,7 +140,7 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
input logic [LINESIZE-1:0] WriteLine, input logic [LINESIZE-1:0] WriteLine,
input logic [`XLEN-1:0] WritePAdr, input logic [`XLEN-1:0] WritePAdr,
// Output the word, as well as if it is valid // Output the word, as well as if it is valid
output logic [WORDSIZE-1:0] DataWord, output logic [31:0] DataWord, // *** was WORDSIZE-1
output logic DataValid output logic DataValid
); );
@ -202,7 +202,31 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
); );
// Pick the right bits coming out the read line // Pick the right bits coming out the read line
assign DataWord = ReadLineTransformed[ReadOffset]; //assign DataWord = ReadLineTransformed[ReadOffset];
//logic [31:0] tempRD;
always_comb begin
case (OldReadPAdr[4:1])
0: DataWord = ReadLine[31:0];
1: DataWord = ReadLine[47:16];
2: DataWord = ReadLine[63:32];
3: DataWord = ReadLine[79:48];
4: DataWord = ReadLine[95:64];
5: DataWord = ReadLine[111:80];
6: DataWord = ReadLine[127:96];
7: DataWord = ReadLine[143:112];
8: DataWord = ReadLine[159:128];
9: DataWord = ReadLine[175:144];
10: DataWord = ReadLine[191:160];
11: DataWord = ReadLine[207:176];
12: DataWord = ReadLine[223:192];
13: DataWord = ReadLine[239:208];
14: DataWord = ReadLine[255:224];
15: DataWord = {16'b0, ReadLine[255:240]};
endcase
end
genvar i; genvar i;
generate generate
for (i=0; i < LINESIZE/WORDSIZE; i++) begin for (i=0; i < LINESIZE/WORDSIZE; i++) begin

35
wally-pipelined/src/ifu/icache.sv
View File

@ -103,12 +103,12 @@ module icachecontroller #(parameter LINESIZE = 256) (
// Signals to/from cache memory // Signals to/from cache memory
// The read coming out of it // The read coming out of it
input logic [`XLEN-1:0] ICacheMemReadData, input logic [31:0] ICacheMemReadData,
input logic ICacheMemReadValid, input logic ICacheMemReadValid,
// The address at which we want to search the cache memory // The address at which we want to search the cache memory
output logic [`XLEN-1:12] ICacheMemReadUpperPAdr, output logic [`XLEN-1:12] ICacheMemReadUpperPAdr,
output logic [11:0] ICacheMemReadLowerAdr, output logic [11:0] ICacheMemReadLowerAdr,
output logic ICacheReadEn, output logic ICacheReadEn,
// Load data into the cache // Load data into the cache
output logic ICacheMemWriteEnable, output logic ICacheMemWriteEnable,
output logic [LINESIZE-1:0] ICacheMemWriteData, output logic [LINESIZE-1:0] ICacheMemWriteData,
@ -565,30 +565,13 @@ module icachecontroller #(parameter LINESIZE = 256) (
.q(SpillDataBlock0)); .q(SpillDataBlock0));
// use the not quite final PC to do the final selection. // use the not quite final PC to do the final selection.
generate logic [1:1] PCPreFinalF_q;
if( `XLEN == 32) begin flopenr #(1) PCFReg(.clk(clk),
logic [1:1] PCPreFinalF_q; .reset(reset),
flopenr #(1) PCFReg(.clk(clk), .en(~StallF),
.reset(reset), .d(PCPreFinalF[1]),
.en(~StallF), .q(PCPreFinalF_q[1]));
.d(PCPreFinalF[1]), assign FinalInstrRawF = PCPreFinalF_q[1] ? {ICacheMemReadData[31:16], SpillDataBlock0} : ICacheMemReadData;
.q(PCPreFinalF_q[1]));
assign FinalInstrRawF = PCPreFinalF_q[1] ? {SpillDataBlock0, ICacheMemReadData[31:16]} : ICacheMemReadData;
end else begin
logic [2:1] PCPreFinalF_q;
flopenr #(2) PCFReg(.clk(clk),
.reset(reset),
.en(~StallF),
.d(PCPreFinalF[2:1]),
.q(PCPreFinalF_q[2:1]));
mux4 #(32) AlignmentMux(.d0(ICacheMemReadData[31:0]),
.d1(ICacheMemReadData[47:16]),
.d2(ICacheMemReadData[63:32]),
.d3({SpillDataBlock0, ICacheMemReadData[63:48]}),
.s(PCPreFinalF_q[2:1]),
.y(FinalInstrRawF));
end
endgenerate
// There is a frustrating issue on the first access. // There is a frustrating issue on the first access.
// The cache will not contain any valid data but will contain x's on // The cache will not contain any valid data but will contain x's on