forked from Github_Repos/cvw
Fixed bug with the compressed immediate generation. Several formats should zero extend.
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@ -53,10 +53,10 @@ module decompress (
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assign rdp = {2'b01, instr16[4:2]};
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assign rdp = {2'b01, instr16[4:2]};
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// many compressed immediate formats
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// many compressed immediate formats
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assign immCILSP = {{4{instr16[3]}}, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
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assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
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assign immCILSPD = {{3{instr16[4]}}, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
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assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
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assign immCSS = {{4{instr16[8]}}, instr16[8:7], instr16[12:9], 2'b00};
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assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00};
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assign immCSSD = {{3{instr16[9]}}, instr16[9:7], instr16[12:10], 3'b000};
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assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000};
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assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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@ -175,4 +175,4 @@ module decompress (
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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