Merge branch 'main' into coverage4

testbench/tests.vh

@@ -53,9 +53,13 @@ string tvpaths[] = '{
     "lsu",
     "vm64check",
     "pmp",
-    "tlbKP",
     "dcache1",
     "dcache2"
+    "pmpcfg",
+    "pmpcfg1",
+    "pmpcfg2",
+    "tlbKP",
+    "ifuCamlineWrite"
   };
 
   string coremark[] = '{

tests/coverage/pmpcfg.S

@@ -0,0 +1,41 @@
+// pmpcfg part 1
+// Kevin Wan, kewan@hmc.edu, 4/18/2023
+// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
+// See the next part in pmpcfg1.S
+
+#include "WALLY-init-lib.h" 
+main: 
+    li t0, 0x8800000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x88000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x880000000000
+    csrw pmpcfg2, t0
+    li t0, 0x8800000000
+    csrw pmpcfg2, t0
+    li t0, 0x88000000
+    csrw pmpcfg2, t0
+    li t0, 0x880000
+    csrw pmpcfg2, t0
+    li t0, 0x8800
+    csrw pmpcfg2, t0
+    li t0, 0x88
+    csrw pmpcfg2, t0
+    li t0, 0x8800000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x88000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x880000000000
+    csrw pmpcfg0, t0
+    li t0, 0x8800000000
+    csrw pmpcfg0, t0
+    li t0, 0x88000000
+    csrw pmpcfg0, t0
+    li t0, 0x880000
+    csrw pmpcfg0, t0
+    li t0, 0x8800
+    csrw pmpcfg0, t0
+
+
+    j done
+

tests/coverage/pmpcfg1.S

@@ -0,0 +1,48 @@
+// another set of pmpcfg tests. A new file is made because pmpcfg register fields are 
+// locked forever after writing 1 to the lock bit for the first time. 
+
+// Kevin Wan, kewan@hmc.edu, 4/13/2023
+// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. 
+// for the other part of the tests, see pmpcfg.S
+
+#include "WALLY-init-lib.h" 
+main: 
+    li t0, 0x800
+    csrw pmpcfg0, t0
+    li t0, 0x8000000
+    csrw pmpcfg0, t0
+
+    li t0, 0x8000000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x80000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x800000000000
+    csrw pmpcfg2, t0
+    li t0, 0x8000000000
+    csrw pmpcfg2, t0
+    li t0, 0x80000000
+    csrw pmpcfg2, t0
+    li t0, 0x800000
+    csrw pmpcfg2, t0
+    li t0, 0x8000
+    csrw pmpcfg2, t0
+    li t0, 0x80
+    csrw pmpcfg2, t0
+    li t0, 0x8000000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x80000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x800000000000
+    csrw pmpcfg0, t0
+    li t0, 0x8000000000
+    csrw pmpcfg0, t0
+    li t0, 0x80000000
+    csrw pmpcfg0, t0
+    li t0, 0x800000
+    csrw pmpcfg0, t0
+    li t0, 0x8000
+    csrw pmpcfg0, t0
+
+
+
+    j done

tests/coverage/pmpcfg2.S

@@ -0,0 +1,12 @@
+// pmpcfg part 3
+// Kevin Wan, kewan@hmc.edu, 4/18/2023
+// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
+// See the next part in pmpcfg1.S
+
+#include "WALLY-init-lib.h" 
+main: 
+    li t0, 0x80
+    csrw pmpcfg0, t0
+
+
+    j done

tests/coverage/priv.S

@@ -189,6 +189,7 @@ main:
     li t1, -1
     csrw mcounteren, t1
 
+
     # Go to supervisor mode
     li a0, 1
     ecall