Enable linting of blocks not yet in the hierarchy

This commit is contained in:
Jarred Allen 2021-04-15 21:13:40 -04:00
parent 81c02bda55
commit 7854d838c7

View File

@ -1,11 +1,25 @@
# check for warnings in Verilog code # check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first. # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
echo "rv64ic linting..." if [ -n "$1" ]; then
verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv echo "rv64ic linting..."
echo "rv32ic linting..." if verilator --lint-only --top-module "$1" -Iconfig/rv64ic src/*/*.sv; then
verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv echo "rv32ic linting..."
#verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv src/*/div/*.sv verilator --lint-only --top-module "$1" -Iconfig/rv32ic src/*/*.sv
else
echo "Skipping rv32ic because rv64ic had errors or warnings"
exit 1
fi
else
echo "rv64ic linting..."
if verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv; then
echo "rv32ic linting..."
verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv
else
echo "Skipping rv32ic because rv64ic had errors or warnings"
exit 1
fi
fi
# --lint-only just runs lint rather than trying to compile and simulate # --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include wally-config.vh are found # -I points to the include directory where files such as `include wally-config.vh are found