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Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail

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David Harris 2022-02-08 12:40:02 +00:00
parent c61cd55c5c
commit 76dccbad91
1 changed files with 1 additions and 1 deletions
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pipelined/testbench/testbench.sv
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@ -256,7 +256,7 @@ logic [3:0] dummy;
if (signature[i] !== sig & if (signature[i] !== sig &
//if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] & //if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1?
if ((signature[i] !== '0 & signature[i+4] != 'x)) begin if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin
// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin // if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin
// report errors unless they are garbage at the end of the sim // report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now // kind of hacky test for garbage right now