Merge branch 'main' of https://github.com/openhwgroup/cvw

README.md

@@ -34,8 +34,8 @@ Clone your fork of the repo and run the setup script.
 
 	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
-	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ cd cvw
+	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ source ./setup.sh
 
 Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.

sim/Makefile

@@ -1,5 +1,5 @@
 
-all: riscoftests memfiles
+all: riscoftests memfiles coveragetests
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
 	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
@@ -50,3 +50,6 @@ riscoftests:
 	make -C ../tests/riscof/ 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
+
+coveragetests:
+	make -C ../tests/coverage/

src/mmu/mmu.sv

@@ -108,12 +108,12 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
-  if (`PMP_ENTRIES > 0) 
+  if (`PMP_ENTRIES > 0) begin : pmp
     pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
       .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
-  else begin
+  end else begin
     assign PMPInstrAccessFaultF     = 0;
     assign PMPStoreAmoAccessFaultM  = 0;
     assign PMPLoadAccessFaultM      = 0;

src/mmu/pmpadrdec.sv

@@ -38,7 +38,7 @@ module pmpadrdec (
   input  logic [`PA_BITS-3:0]      PMPAdr,
   input  logic                  PAgePMPAdrIn,
   output logic                  PAgePMPAdrOut,
-  output logic                  Match, Active, 
+  output logic                  Match, 
   output logic                  L, X, W, R
 );
   
@@ -84,7 +84,6 @@ module pmpadrdec (
   assign X = PMPCfg[2];
   assign W = PMPCfg[1];
   assign R = PMPCfg[0];
-  assign Active = |PMPCfg[4:3];
 
   // known bug: The size of the access is not yet checked.  For example, if an NA4 entry matches 0xC-0xF and the system
   // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This

src/mmu/pmpchecker.sv

@@ -53,25 +53,23 @@ module pmpchecker (
   logic                    EnforcePMP; // should PMP be checked in this privilege level
   logic [`PMP_ENTRIES-1:0] Match;      // physical address matches one of the pmp ranges
   logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-  logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
   logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
   logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
-  if (`PMP_ENTRIES > 0) // prevent complaints about array of no elements when PMP_ENTRIES = 0
+  if (`PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
     pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
       .PhysicalAddress, 
       .PMPCfg(PMPCFG_ARRAY_REGW),
       .PMPAdr(PMPADDR_ARRAY_REGW),
       .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
       .PAgePMPAdrOut(PAgePMPAdr),
-      .Match, .Active, .L, .X, .W, .R);
+      .Match, .L, .X, .W, .R);
+  end
 
   priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
   // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
+  assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
-//  assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
-//  *** remove unused Active lines from pmpadrdecs
 
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
   assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;

src/privileged/csrs.sv

@@ -131,7 +131,7 @@ module csrs #(parameter
       SATP:      if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
                  else begin
                    CSRSReadValM = 0;
-                   if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;
+                   IllegalCSRSAccessM = 1;
                  end
       SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW};
       STIMECMP:  if (`SSTC_SUPPORTED & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[`XLEN-1:0]; 

testbench/testbench-fp.sv

@@ -702,7 +702,7 @@ module testbenchfp;
   
   if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
     fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
-              .XZero(XZero), .XSubnorm(XSubnorm), .OpCtrl(OpCtrlVal), .IntZero,
+              .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
               .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
   end
 

testbench/tests-fp.vh

@@ -24,7 +24,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`define PATH "../../tests/fp/vectors/"
+`define PATH "../tests/fp/vectors/"
 `define ADD_OPCTRL 3'b110
 `define MUL_OPCTRL 3'b100
 `define SUB_OPCTRL 3'b111

testbench/tests.vh

@@ -46,7 +46,8 @@ string tvpaths[] = '{
     `COVERAGE,
     "ieu",
     "ebu",
-    "csrwrites"
+    "csrwrites",
+    "priv"
   };
 
   string coremark[] = '{
@@ -1963,17 +1964,19 @@ string arch64zbs[] = '{
     "rv32i_m/privilege/src/WALLY-trap-u-01.S",
     "rv32i_m/privilege/src/WALLY-wfi-01.S",
     "rv32i_m/privilege/src/WALLY-endianness-01.S",
-    "rv32i_m/privilege/src/WALLY-satp-invalid-01.S"
+    "rv32i_m/privilege/src/WALLY-satp-invalid-01.S",
- };
+    // These peripherals are here instead of wally32periph because they don't work on rv32imc, which lacks a PMP register to configure
-
- string wally32periph[] = '{
-    `WALLYTEST,
-    "rv32i_m/privilege/src/WALLY-periph-01.S",
     "rv32i_m/privilege/src/WALLY-gpio-01.S",
     "rv32i_m/privilege/src/WALLY-clint-01.S",
     "rv32i_m/privilege/src/WALLY-uart-01.S",
     "rv32i_m/privilege/src/WALLY-plic-01.S",
     "rv32i_m/privilege/src/WALLY-plic-s-01.S"
+
+ };
+
+ string wally32periph[] = '{
+    `WALLYTEST,
+    "rv32i_m/privilege/src/WALLY-periph-01.S"
  };
 
 

tests/coverage/WALLY-init-lib.h

@@ -40,6 +40,10 @@ rvtest_entry_point:
     la t0, topoftrapstack 
     csrw mscratch, t0   # MSCRATCH holds trap stack pointer
     csrsi mstatus, 0x8  # Turn on mstatus.MIE global interrupt enable
+    # set up PMP so user and supervisor mode can access full address space
+    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
+    li t0, 0xFFFFFFFF   
+    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
     j main              # Call main function in user test program
 
 done:

tests/coverage/priv.S

@@ -0,0 +1,39 @@
+///////////////////////////////////////////
+// priv.S
+//
+// Written: David_Harris@hmc.edu 23 March 2023
+//
+// Purpose: Test coverage for EBU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+#include "WALLY-init-lib.h"
+
+main:
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    # Test read to stimecmp fails when MCOUNTEREN_TM is not set
+    addi t0, zero, 0
+    csrr t0, stimecmp 
+
+    j done

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output

@@ -6,16 +6,16 @@
 00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-8000015c # mtval of breakpoint instruction adress
+80000168 # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000165 # mtval of misaligned address
+80000171 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-8000017d # mtval of address with misaligned store instr
+80000189 # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)
@@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-8000015c # mtval of breakpoint instruction adress
+80000168 # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000165 # mtval of misaligned address
+80000171 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-8000017d # mtval of address with misaligned store instr
+80000189 # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -9,16 +9,16 @@
 00000000 # stval of faulting instruction (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-8000015c # stval of breakpoint instruction adress
+80000168 # stval of breakpoint instruction adress
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000165 # stval of misaligned address
+80000171 # stval of misaligned address
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-8000017d # stval of address with misaligned store instr
+80000189 # stval of address with misaligned store instr
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -60,16 +60,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # stval of faulting instruction (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-8000015c # stval of breakpoint instruction adress
+80000168 # stval of breakpoint instruction adress
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000165 # stval of misaligned address
+80000171 # stval of misaligned address
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-8000017d # stval of address with misaligned store instr
+80000189 # stval of address with misaligned store instr
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -9,16 +9,16 @@
 00000000 # stval of faulting instruction (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-8000015c # stval of breakpoint instruction adress
+80000168 # stval of breakpoint instruction adress
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000165 # stval of misaligned address
+80000171 # stval of misaligned address
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-8000017d # stval of address with misaligned store instr
+80000189 # stval of address with misaligned store instr
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # stval of faulting instruction (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-8000015c # stval of breakpoint instruction adress
+80000168 # stval of breakpoint instruction adress
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000165 # stval of misaligned address
+80000171 # stval of misaligned address
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-8000017d # stval of address with misaligned store instr
+80000189 # stval of address with misaligned store instr
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -55,6 +55,12 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
+    // set up PMP so user and supervisor mode can access full address space
+    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
+    li t0, 0xFFFFFFFF   
+    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
+
+
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output

@@ -14,13 +14,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003f4 # mtval of breakpoint instruction adress (0x80000400)
+80000408 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003fd # mtval of misaligned address (0x80000409)
+80000411 # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -32,7 +32,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000415 # mtval of address with misaligned store instr (0x80000421)
+80000429 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -126,13 +126,13 @@ ffffffff
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003f4 # mtval of breakpoint instruction adress (0x80000400)
+80000408 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003fd # mtval of misaligned address (0x80000409)
+80000411 # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -144,7 +144,7 @@ ffffffff
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000415 # mtval of address with misaligned store instr (0x80000421)
+80000429 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -20,13 +20,13 @@
 00000000
 00000003 # scause from Breakpoint
 00000000
-800003f4 # stval of breakpoint instruction adress (0x80000400)
+80000408 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-800003fd # stval of misaligned address (0x80000409)
+80000411 # stval of misaligned address (0x80000409)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@
 00000000
 00000006 # scause from store misaligned
 00000000
-80000415 # stval of address with misaligned store instr (0x80000421)
+80000429 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -122,13 +122,13 @@ ffffffff
 00000000
 00000003 # scause from Breakpoint
 00000000
-800003f4 # stval of breakpoint instruction adress (0x80000400)
+80000408 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-800003fd # stval of misaligned address (0x80000409)
+80000411 # stval of misaligned address (0x80000409)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -140,7 +140,7 @@ ffffffff
 00000000
 00000006 # scause from store misaligned
 00000000
-80000415 # stval of address with misaligned store instr (0x80000421)
+80000429 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -20,13 +20,13 @@
 00000000
 00000003 # scause from Breakpoint
 00000000
-800003f4 # stval of breakpoint instruction adress (0x80000400)
+80000408 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-800003fd # stval of misaligned address (0x80000409)
+80000411 # stval of misaligned address (0x80000409)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@
 00000000
 00000006 # scause from store misaligned
 00000000
-80000415 # stval of address with misaligned store instr (0x80000421)
+80000429 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -116,13 +116,13 @@ ffffffff
 00000000
 00000003 # scause from Breakpoint
 00000000
-800003f4 # stval of breakpoint instruction adress (0x80000400)
+80000408 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-800003fd # stval of misaligned address (0x80000409)
+80000411 # stval of misaligned address (0x80000409)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -134,7 +134,7 @@ ffffffff
 00000000
 00000006 # scause from store misaligned
 00000000
-80000415 # stval of address with misaligned store instr (0x80000421)
+80000429 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -57,6 +57,11 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
+    // set up PMP so user and supervisor mode can access full address space
+    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
+    li t0, 0xFFFFFFFF   
+    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
+
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses