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Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill.

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This commit is contained in:
Ross Thompson 2023-01-18 19:10:34 -06:00
parent 026d09b79b
commit 7289fa8d44
2 changed files with 11 additions and 7 deletions
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13
pipelined/src/ifu/irom.sv
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@ -36,15 +36,20 @@ module irom(
localparam OFFSET = $clog2(`XLEN/8); localparam OFFSET = $clog2(`XLEN/8);
logic [`XLEN-1:0] IROMInstrFFull; logic [`XLEN-1:0] IROMInstrFFull;
logic [31:0] RawIROMInstrF;
logic [1:0] AdrD;
flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
if (`XLEN == 32) assign IROMInstrF = IROMInstrFFull; if (`XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
else begin else begin
// IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two // IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two
// haves. Adr is the Next PCF not PCF so we delay 1 cycle. // haves. Adr is the Next PCF not PCF so we delay 1 cycle.
logic AdrD; assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
assign IROMInstrF = AdrD ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
end end
// If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
// The spill logic will handle merging the two together.
assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
endmodule endmodule

5
pipelined/src/ifu/spillsupport.sv
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@ -51,7 +51,7 @@ module spillsupport #(parameter CACHE_ENABLED)
logic TakeSpillF; logic TakeSpillF;
logic SpillF; logic SpillF;
logic SelSpillF, SpillSaveF; logic SelSpillF, SpillSaveF;
logic [15:0] SpillDataLine0, SavedInstr; logic [15:0] SpillDataLine0;
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
@ -83,12 +83,11 @@ module spillsupport #(parameter CACHE_ENABLED)
assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
(CurrState == STATE_SPILL & IFUCacheBusStallD); (CurrState == STATE_SPILL & IFUCacheBusStallD);
assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF; assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];
flopenr #(16) SpillInstrReg(.clk(clk), flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSaveF & ~Flush), .en(SpillSaveF & ~Flush),
.reset(reset), .reset(reset),
.d(SavedInstr), .d(InstrRawF[15:0]),
.q(SpillDataLine0)); .q(SpillDataLine0));
mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF), mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),