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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-10-27 14:40:31 -07:00
commit 7158bf1d4f
25 changed files with 722 additions and 600 deletions
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2
README.md
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@ -14,6 +14,8 @@ cd ../addins
git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-non-isa/riscv-arch-test
git clone https://github.com/riscv-software-src/riscv-isa-sim git clone https://github.com/riscv-software-src/riscv-isa-sim
cd riscv-isa-sim cd riscv-isa-sim
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
mkdir build mkdir build
cd build cd build
set RISCV=/cad/riscv/gcc/bin (or whatever your path is) set RISCV=/cad/riscv/gcc/bin (or whatever your path is)

1
wally-pipelined/regression/regression-wally.py
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@ -48,6 +48,7 @@ for test in tests64:
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!", cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
#tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
for test in tests32: for test in tests32:
tc = TestCase( tc = TestCase(

2
wally-pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv32g arch32m" vsim -do "do wally-pipelined.do rv32g arch32f"

2
wally-pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-pipelined-batch.do rv64g arch64m do wally-pipelined-batch.do rv32g arch32f
! !

2
wally-pipelined/regression/wave-dos/peripheral-waves.do
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@ -53,7 +53,7 @@ add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
add wave -divider add wave -divider
add wave -hex /testbench/PCW add wave -hex /testbench/PCW
#add wave -hex /testbench/InstrW #add wave -hex /testbench/InstrW
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW #add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
#add wave /testbench/InstrWName #add wave /testbench/InstrWName
add wave -hex /testbench/dut/hart/ReadDataW add wave -hex /testbench/dut/hart/ReadDataW
add wave -hex /testbench/dut/hart/ieu/dp/ResultW add wave -hex /testbench/dut/hart/ieu/dp/ResultW

2
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -49,7 +49,7 @@ module cachereplacementpolicy
logic LRUWriteEnD; logic LRUWriteEnD;
/* verilator lint_off BLKLOOPINIT */ /* verilator lint_off BLKLOOPINIT */
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk) begin
if (reset) begin if (reset) begin
RAdrD <= '0; RAdrD <= '0;
MemPAdrMD <= '0; MemPAdrMD <= '0;

6
wally-pipelined/src/cache/cacheway.sv vendored
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@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay; assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk) begin
if (reset) if (reset)
ValidBits <= {NUMLINES{1'b0}}; ValidBits <= {NUMLINES{1'b0}};
else if (InvalidateAll) else if (InvalidateAll)
@ -134,14 +134,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
generate generate
if(DIRTY_BITS) begin if(DIRTY_BITS) begin
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk) begin
if (reset) if (reset)
DirtyBits <= {NUMLINES{1'b0}}; DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1; else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
end end
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk) begin
SetDirtyD <= SetDirty; SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty; ClearDirtyD <= ClearDirty;
end end

2
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -144,7 +144,7 @@ module dcachefsm
assign CntEn = PreCntEn & AHBAck; assign CntEn = PreCntEn & AHBAck;
always_ff @(posedge clk, posedge reset) always_ff @(posedge clk)
if (reset) CurrState <= #1 STATE_READY; if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState; else CurrState <= #1 NextState;

2
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -116,7 +116,7 @@ module icachefsm
logic PreCntEn; logic PreCntEn;
// the FSM is always runing, do not stall. // the FSM is always runing, do not stall.
always_ff @(posedge clk, posedge reset) always_ff @(posedge clk)
if (reset) CurrState <= #1 STATE_READY; if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState; else CurrState <= #1 NextState;

4
wally-pipelined/src/fpu/fpu.sv
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@ -41,7 +41,7 @@ module fpu (
output logic [`XLEN-1:0] FIntResM, // data to be written to integer register output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
output logic [4:0] SetFflagsM // FMA flags (to privileged unit) output logic [4:0] SetFflagsM // FPU flags (to privileged unit)
); );
//*** make everything FLEN at some point //*** make everything FLEN at some point
@ -267,7 +267,7 @@ module fpu (
// BEGIN MEMORY STAGE // BEGIN MEMORY STAGE
// FPU flag selection - to privileged // FPU flag selection - to privileged
mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM); mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
// M/W pipe registers // M/W pipe registers
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);

60
wally-pipelined/src/ifu/BTBPredictor.sv
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@ -31,25 +31,25 @@
module BTBPredictor module BTBPredictor
#(parameter int Depth = 10 #(parameter int Depth = 10
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [`XLEN-1:0] TargetPC, output logic [`XLEN-1:0] TargetPC,
output logic [4:0] InstrClass, output logic [4:0] InstrClass,
output logic Valid, output logic Valid,
// update // update
input logic UpdateEN, input logic UpdateEN,
input logic [`XLEN-1:0] UpdatePC, input logic [`XLEN-1:0] UpdatePC,
input logic [`XLEN-1:0] UpdateTarget, input logic [`XLEN-1:0] UpdateTarget,
input logic [4:0] UpdateInstrClass, input logic [4:0] UpdateInstrClass,
input logic UpdateInvalid input logic UpdateInvalid
); );
localparam TotalDepth = 2 ** Depth; localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits; logic [TotalDepth-1:0] ValidBits;
logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ; logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
logic UpdateENQ; logic UpdateENQ;
// hashing function for indexing the PC // hashing function for indexing the PC
@ -61,10 +61,10 @@ module BTBPredictor
flopenr #(Depth) UpdatePCIndexReg(.clk(clk), flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.d(UpdatePCIndex), .d(UpdatePCIndex),
.q(UpdatePCIndexQ)); .q(UpdatePCIndexQ));
// The valid bit must be resetable. // The valid bit must be resetable.
always_ff @ (posedge clk) begin always_ff @ (posedge clk) begin
@ -79,17 +79,17 @@ module BTBPredictor
flopenr #(1) UpdateENReg(.clk(clk), flopenr #(1) UpdateENReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallF), .en(~StallF),
.d(UpdateEN), .d(UpdateEN),
.q(UpdateENQ)); .q(UpdateENQ));
flopenr #(Depth) LookupPCIndexReg(.clk(clk), flopenr #(Depth) LookupPCIndexReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallF), .en(~StallF),
.d(LookUpPCIndex), .d(LookUpPCIndex),
.q(LookUpPCIndexQ)); .q(LookUpPCIndexQ));
@ -98,14 +98,14 @@ module BTBPredictor
// *** need to add forwarding. // *** need to add forwarding.
SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk), SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk),
.reset(reset), .reset(reset),
.RA1(LookUpPCIndex), .RA1(LookUpPCIndex),
.RD1({{InstrClass, TargetPC}}), .RD1({{InstrClass, TargetPC}}),
.REN1(~StallF), .REN1(~StallF),
.WA1(UpdatePCIndex), .WA1(UpdatePCIndex),
.WD1({UpdateInstrClass, UpdateTarget}), .WD1({UpdateInstrClass, UpdateTarget}),
.WEN1(UpdateEN), .WEN1(UpdateEN),
.BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right. .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
endmodule endmodule

98
wally-pipelined/src/ifu/CodeAligner.py Normal file
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@ -0,0 +1,98 @@
import os
# Kevin Wan kewan@hmc.edu 10/27/2021
def read_input(filename): #1
"""Takes in a string filename and outputs the parsed verilog code by line into a list
such that each element of the list is one line of verilog code as a string."""
lineOfCode = []
input_file = open(filename, 'r')
for line in input_file:
lineOfCode.append(line)
return lineOfCode
###################################################################################
def ID_start(GiantString):#2
"""takes in the list of sv file lines, outputs the location that variable names should start"""
VarLoc = 0
VarLineNum = None
for lines in GiantString:
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines:# need to account for these space
NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines) # Update this number if new record is made.
else:
NowLoc = lines.find('logic') + 7 # same as before.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines)
#print("Furthest variable appears on line", VarLineNum + 1,VarLoc) # Disable this line after debugging.
return VarLoc
##################################################################################
def modified_logNew(GS,SOV): #3
Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it.
Out = []
for l in GS:
lines = l.replace('\t',' ')
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines: # the line is an extended declaration.
EditLoc = lines.find("]") # Re-finds the string index number of ].
VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1 # Checks where variable declaration currently is at.
#print(VarLoc,lines[VarLoc])# VERIFIED
NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind)
Out.append(NewLine)# Verified0957 10272021
else:
EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
Out.append(NewLine1)# Verified 1005 10272021
else:
Out.append(lines)
return Out
################################################################################
def write_to_output(filename,GiantString,OW=True,Lines_editted=None): #4
"""Filename is preferrably passed from the early function calls"""
"""GiantString has all the corrected features in the code, each line is a good verilog code line"""
newname = filename
if not OW or OW =='f': #which means no overwrite (create a new file)
Decomposed=filename.split('.')
newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned.
OutFile = open(newname,'w') # This step should create a new file.
OutFile.writelines(GiantString)
OutFile.close()
print("Success! " + newname + " Now contains an aligned file!")
return newname
#################################################################################
def FindCharRel(Ln):
#returns the computer location of a character's first occurence
for num in range(len(Ln)):
if Ln[num] != " ":
return num
def Mod_Space_at(Ln,loc,diff):
#loc is the varLoc from mln, diff is varLoc - Ind
if diff > 0: # to delete
NewString = Ln[:(loc-diff)] + Ln[loc:]
if diff < 0: # to add
NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
if diff == 0:
NewString = Ln
return NewString
def main_filehandler(overwrite=False):
for filename in os.listdir():
if ".py" not in filename:
GiantString = read_input(filename)
SOV = ID_start(GiantString)
ModifiedGS = modified_logNew(GiantString,SOV)
Newname = write_to_output(filename,ModifiedGS,overwrite)
main_filehandler(True)

30
wally-pipelined/src/ifu/RAsPredictor.sv
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@ -30,21 +30,21 @@
module RASPredictor module RASPredictor
#(parameter int StackSize = 16 #(parameter int StackSize = 16
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic pop, input logic pop,
output logic [`XLEN-1:0] popPC, output logic [`XLEN-1:0] popPC,
input logic push, input logic push,
input logic incr, input logic incr,
input logic [`XLEN-1:0] pushPC input logic [`XLEN-1:0] pushPC
); );
logic CounterEn; logic CounterEn;
localparam Depth = $clog2(StackSize); localparam Depth = $clog2(StackSize);
logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1;
logic [StackSize-1:0] [`XLEN-1:0] memory; logic [StackSize-1:0] [`XLEN-1:0] memory;
integer index; integer index;
assign CounterEn = pop | push | incr; assign CounterEn = pop | push | incr;
@ -56,16 +56,16 @@ module RASPredictor
// *** what happens if jal is executing and there is a return being flushed in Decode? // *** what happens if jal is executing and there is a return being flushed in Decode?
flopenr #(Depth) PTR(.clk(clk), flopenr #(Depth) PTR(.clk(clk),
.reset(reset), .reset(reset),
.en(CounterEn), .en(CounterEn),
.d(PtrD), .d(PtrD),
.q(PtrQ)); .q(PtrQ));
// RAS must be reset. // RAS must be reset.
always_ff @ (posedge clk, posedge reset) begin always_ff @ (posedge clk) begin
if(reset) begin if(reset) begin
for(index=0; index<StackSize; index++) for(index=0; index<StackSize; index++)
memory[index] <= {`XLEN{1'b0}}; memory[index] <= {`XLEN{1'b0}};
end else if(push) begin end else if(push) begin
memory[PtrP1] <= #1 pushPC; memory[PtrP1] <= #1 pushPC;
end end

56
wally-pipelined/src/ifu/SRAM2P1R1W.sv
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@ -40,68 +40,68 @@ module SRAM2P1R1W
parameter int WIDTH = 2 parameter int WIDTH = 2
) )
(input logic clk, (input logic clk,
// *** have to remove reset eventually // *** have to remove reset eventually
input logic reset, input logic reset,
// port 1 is read only // port 1 is read only
input logic [DEPTH-1:0] RA1, input logic [DEPTH-1:0] RA1,
output logic [WIDTH-1:0] RD1, output logic [WIDTH-1:0] RD1,
input logic REN1, input logic REN1,
// port 2 is write only // port 2 is write only
input logic [DEPTH-1:0] WA1, input logic [DEPTH-1:0] WA1,
input logic [WIDTH-1:0] WD1, input logic [WIDTH-1:0] WD1,
input logic WEN1, input logic WEN1,
input logic [WIDTH-1:0] BitWEN1 input logic [WIDTH-1:0] BitWEN1
); );
logic [DEPTH-1:0] RA1Q, WA1Q; logic [DEPTH-1:0] RA1Q, WA1Q;
logic WEN1Q; logic WEN1Q;
logic [WIDTH-1:0] WD1Q; logic [WIDTH-1:0] WD1Q;
logic [WIDTH-1:0] mem[2**DEPTH-1:0]; logic [WIDTH-1:0] mem[2**DEPTH-1:0];
// SRAMs address busses are always registered first. // SRAMs address busses are always registered first.
flopenr #(DEPTH) RA1Reg(.clk(clk), flopenr #(DEPTH) RA1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(RA1), .d(RA1),
.q(RA1Q)); .q(RA1Q));
flopenr #(DEPTH) WA1Reg(.clk(clk), flopenr #(DEPTH) WA1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(WA1), .d(WA1),
.q(WA1Q)); .q(WA1Q));
flopenr #(1) WEN1Reg(.clk(clk), flopenr #(1) WEN1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(1'b1), .en(1'b1),
.d(WEN1), .d(WEN1),
.q(WEN1Q)); .q(WEN1Q));
flopenr #(WIDTH) WD1Reg(.clk(clk), flopenr #(WIDTH) WD1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(WD1), .d(WD1),
.q(WD1Q)); .q(WD1Q));
// read port // read port
assign RD1 = mem[RA1Q]; assign RD1 = mem[RA1Q];
genvar index; genvar index;
// write port // write port
generate generate
for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite
always_ff @ (posedge clk) begin always_ff @ (posedge clk) begin
if (WEN1Q & BitWEN1[index]) begin if (WEN1Q & BitWEN1[index]) begin
mem[WA1Q][index] <= WD1Q[index]; mem[WA1Q][index] <= WD1Q[index];
end end
end end
end end
endgenerate endgenerate

216
wally-pipelined/src/ifu/bpred.sv
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@ -29,43 +29,43 @@
`include "wally-config.vh" `include "wally-config.vh"
module bpred module bpred
(input logic clk, reset, (input logic clk, reset,
input logic StallF, StallD, StallE, input logic StallF, StallD, StallE,
input logic FlushF, FlushD, FlushE, input logic FlushF, FlushD, FlushE,
// Fetch stage // Fetch stage
// the prediction // the prediction
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
output logic [`XLEN-1:0] BPPredPCF, output logic [`XLEN-1:0] BPPredPCF,
output logic SelBPPredF, output logic SelBPPredF,
// Update Predictor // Update Predictor
input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
// 1 hot encoding // 1 hot encoding
// return, jump register, jump, branch // return, jump register, jump, branch
// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class. // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
// *** the specifics of how this is encode is subject to change. // *** the specifics of how this is encode is subject to change.
input logic PCSrcE, // AKA Branch Taken input logic PCSrcE, // AKA Branch Taken
// Signals required to check the branch prediction accuracy. // Signals required to check the branch prediction accuracy.
input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken. input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken.
input logic [`XLEN-1:0] PCD, // The address the branch predictor took. input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
input logic [4:0] InstrClassE, input logic [4:0] InstrClassE,
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE, output logic BPPredWrongE,
output logic BPPredDirWrongE, output logic BPPredDirWrongE,
output logic BTBPredPCWrongE, output logic BTBPredPCWrongE,
output logic RASPredPCWrongE, output logic RASPredPCWrongE,
output logic BPPredClassNonCFIWrongE output logic BPPredClassNonCFIWrongE
); );
logic BTBValidF; logic BTBValidF;
logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE; logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE;
logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE; logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE;
logic [`XLEN-1:0] BTBPredPCF, RASPCF; logic [`XLEN-1:0] BTBPredPCF, RASPCF;
logic TargetWrongE; logic TargetWrongE;
logic FallThroughWrongE; logic FallThroughWrongE;
logic PredictionPCWrongE; logic PredictionPCWrongE;
logic PredictionInstrClassWrongE; logic PredictionInstrClassWrongE;
// Part 1 branch direction prediction // Part 1 branch direction prediction
@ -73,69 +73,69 @@ module bpred
generate generate
if (`BPTYPE == "BPTWOBIT") begin:Predictor if (`BPTYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk(clk), twoBitPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.StallF(StallF), .StallF(StallF),
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update
.UpdatePC(PCE), .UpdatePC(PCE),
.UpdateEN(InstrClassE[0] & ~StallE), .UpdateEN(InstrClassE[0] & ~StallE),
.UpdatePrediction(UpdateBPPredE)); .UpdatePrediction(UpdateBPPredE));
end else if (`BPTYPE == "BPGLOBAL") begin:Predictor end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
globalHistoryPredictor DirPredictor(.clk(clk), globalHistoryPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.*, // Stalls and flushes .*, // Stalls and flushes
.PCNextF(PCNextF), .PCNextF(PCNextF),
.BPPredF(BPPredF), .BPPredF(BPPredF),
// update // update
.InstrClassE(InstrClassE), .InstrClassE(InstrClassE),
.BPInstrClassE(BPInstrClassE), .BPInstrClassE(BPInstrClassE),
.BPPredDirWrongE(BPPredDirWrongE), .BPPredDirWrongE(BPPredDirWrongE),
.PCE(PCE), .PCE(PCE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.UpdateBPPredE(UpdateBPPredE)); .UpdateBPPredE(UpdateBPPredE));
end else if (`BPTYPE == "BPGSHARE") begin:Predictor end else if (`BPTYPE == "BPGSHARE") begin:Predictor
gsharePredictor DirPredictor(.clk(clk), gsharePredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.*, // Stalls and flushes .*, // Stalls and flushes
.PCNextF(PCNextF), .PCNextF(PCNextF),
.BPPredF(BPPredF), .BPPredF(BPPredF),
// update // update
.InstrClassE(InstrClassE), .InstrClassE(InstrClassE),
.BPInstrClassE(BPInstrClassE), .BPInstrClassE(BPInstrClassE),
.BPPredDirWrongE(BPPredDirWrongE), .BPPredDirWrongE(BPPredDirWrongE),
.PCE(PCE), .PCE(PCE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.UpdateBPPredE(UpdateBPPredE)); .UpdateBPPredE(UpdateBPPredE));
end end
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk(clk), localHistoryPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.*, // Stalls and flushes .*, // Stalls and flushes
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update
.UpdatePC(PCE), .UpdatePC(PCE),
.UpdateEN(InstrClassE[0] & ~StallE), .UpdateEN(InstrClassE[0] & ~StallE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.UpdatePrediction(UpdateBPPredE)); .UpdatePrediction(UpdateBPPredE));
end end
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk(clk), localHistoryPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.*, // Stalls and flushes .*, // Stalls and flushes
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update
.UpdatePC(PCE), .UpdatePC(PCE),
.UpdateEN(InstrClassE[0] & ~StallE), .UpdateEN(InstrClassE[0] & ~StallE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.UpdatePrediction(UpdateBPPredE)); .UpdatePrediction(UpdateBPPredE));
end end
endgenerate endgenerate
@ -146,9 +146,9 @@ module bpred
// For a 2 bit table this is the prediction count. // For a 2 bit table this is the prediction count.
assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) |
BPInstrClassF[3] | BPInstrClassF[3] |
(BPInstrClassF[2] & BTBValidF) | (BPInstrClassF[2] & BTBValidF) |
BPInstrClassF[1] & BTBValidF) ; BPInstrClassF[1] & BTBValidF) ;
// Part 2 Branch target address prediction // Part 2 Branch target address prediction
@ -156,28 +156,28 @@ module bpred
// *** getting to many false positivies from the BTB, we need a partial TAG to reduce this. // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
BTBPredictor TargetPredictor(.clk(clk), BTBPredictor TargetPredictor(.clk(clk),
.reset(reset), .reset(reset),
.*, // Stalls and flushes .*, // Stalls and flushes
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.TargetPC(BTBPredPCF), .TargetPC(BTBPredPCF),
.InstrClass(BPInstrClassF), .InstrClass(BPInstrClassF),
.Valid(BTBValidF), .Valid(BTBValidF),
// update // update
.UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
.UpdatePC(PCE), .UpdatePC(PCE),
.UpdateTarget(PCTargetE), .UpdateTarget(PCTargetE),
.UpdateInvalid(PredictionInstrClassWrongE), .UpdateInvalid(PredictionInstrClassWrongE),
.UpdateInstrClass(InstrClassE)); .UpdateInstrClass(InstrClassE));
// Part 3 RAS // Part 3 RAS
// *** need to add the logic to restore RAS on flushes. We will use incr for this. // *** need to add the logic to restore RAS on flushes. We will use incr for this.
RASPredictor RASPredictor(.clk(clk), RASPredictor RASPredictor(.clk(clk),
.reset(reset), .reset(reset),
.pop(BPInstrClassF[3] & ~StallF), .pop(BPInstrClassF[3] & ~StallF),
.popPC(RASPCF), .popPC(RASPCF),
.push(InstrClassE[4] & ~StallE), .push(InstrClassE[4] & ~StallE),
.incr(1'b0), .incr(1'b0),
.pushPC(PCLinkE)); .pushPC(PCLinkE));
assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF; assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF;
@ -187,31 +187,31 @@ module bpred
// *** for other predictors will will be different. // *** for other predictors will will be different.
flopenr #(2) BPPredRegD(.clk(clk), flopenr #(2) BPPredRegD(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallD), .en(~StallD),
.d(BPPredF), .d(BPPredF),
.q(BPPredD)); .q(BPPredD));
flopenr #(2) BPPredRegE(.clk(clk), flopenr #(2) BPPredRegE(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.d(BPPredD), .d(BPPredD),
.q(BPPredE)); .q(BPPredE));
// pipeline the class // pipeline the class
flopenrc #(5) InstrClassRegD(.clk(clk), flopenrc #(5) InstrClassRegD(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallD), .en(~StallD),
.clear(FlushD), .clear(FlushD),
.d(BPInstrClassF), .d(BPInstrClassF),
.q(BPInstrClassD)); .q(BPInstrClassD));
flopenrc #(5) InstrClassRegE(.clk(clk), flopenrc #(5) InstrClassRegE(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.clear(FlushE), .clear(FlushE),
.d(BPInstrClassD), .d(BPInstrClassD),
.q(BPInstrClassE)); .q(BPInstrClassE));
@ -253,7 +253,7 @@ module bpred
// Update predictors // Update predictors
satCounter2 BPDirUpdate(.BrDir(PCSrcE), satCounter2 BPDirUpdate(.BrDir(PCSrcE),
.OldState(BPPredE), .OldState(BPPredE),
.NewState(UpdateBPPredE)); .NewState(UpdateBPPredE));
endmodule endmodule

18
wally-pipelined/src/ifu/decompress.sv
View File

@ -26,16 +26,16 @@
`include "wally-config.vh" `include "wally-config.vh"
module decompress ( module decompress (
input logic [31:0] InstrRawD, input logic [31:0] InstrRawD,
output logic [31:0] InstrD, output logic [31:0] InstrD,
output logic IllegalCompInstrD); output logic IllegalCompInstrD);
logic [15:0] instr16; logic [15:0] instr16;
logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp; logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp;
logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW; logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
logic [19:0] immCJ, immCILUI; logic [19:0] immCJ, immCILUI;
logic [5:0] immSH; logic [5:0] immSH;
logic [1:0] op; logic [1:0] op;
// if the system handles compressed instructions, decode appropriately // if the system handles compressed instructions, decode appropriately
generate generate

70
wally-pipelined/src/ifu/globalHistoryPredictor.sv
View File

@ -30,35 +30,35 @@
module globalHistoryPredictor module globalHistoryPredictor
#(parameter int k = 10 #(parameter int k = 10
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
output logic [1:0] BPPredF, output logic [1:0] BPPredF,
// update // update
input logic [4:0] InstrClassE, input logic [4:0] InstrClassE,
input logic [4:0] BPInstrClassE, input logic [4:0] BPInstrClassE,
input logic [4:0] BPInstrClassD, input logic [4:0] BPInstrClassD,
input logic [4:0] BPInstrClassF, input logic [4:0] BPInstrClassF,
input logic BPPredDirWrongE, input logic BPPredDirWrongE,
input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCE,
input logic PCSrcE, input logic PCSrcE,
input logic [1:0] UpdateBPPredE input logic [1:0] UpdateBPPredE
); );
logic [k+1:0] GHR, GHRNext; logic [k+1:0] GHR, GHRNext;
logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
logic PHTUpdateEN; logic PHTUpdateEN;
logic BPClassWrongNonCFI; logic BPClassWrongNonCFI;
logic BPClassWrongCFI; logic BPClassWrongCFI;
logic BPClassRightNonCFI; logic BPClassRightNonCFI;
logic BPClassRightBPWrong; logic BPClassRightBPWrong;
logic BPClassRightBPRight; logic BPClassRightBPRight;
logic [6:0] GHRMuxSel; logic [6:0] GHRMuxSel;
logic GHRUpdateEN; logic GHRUpdateEN;
logic [k-1:0] GHRLookup; logic [k-1:0] GHRLookup;
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@ -92,10 +92,10 @@ module globalHistoryPredictor
end end
flopenr #(k+2) GlobalHistoryRegister(.clk(clk), flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
.reset(reset), .reset(reset),
.en((GHRUpdateEN)), .en((GHRUpdateEN)),
.d(GHRNext), .d(GHRNext),
.q(GHR)); .q(GHR));
// if actively updating the GHR at the time of prediction we want to us // if actively updating the GHR at the time of prediction we want to us
// GHRNext as the lookup rather than GHR. // GHRNext as the lookup rather than GHR.
@ -109,14 +109,14 @@ module globalHistoryPredictor
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
SRAM2P1R1W #(k, 2) PHT(.clk(clk), SRAM2P1R1W #(k, 2) PHT(.clk(clk),
.reset(reset), .reset(reset),
//.RA1(GHR[k-1:0]), //.RA1(GHR[k-1:0]),
.RA1(GHRLookup), .RA1(GHRLookup),
.RD1(BPPredF), .RD1(BPPredF),
.REN1(~StallF), .REN1(~StallF),
.WA1(PHTUpdateAdr), .WA1(PHTUpdateAdr),
.WD1(UpdateBPPredE), .WD1(UpdateBPPredE),
.WEN1(PHTUpdateEN), .WEN1(PHTUpdateEN),
.BitWEN1(2'b11)); .BitWEN1(2'b11));
endmodule endmodule

70
wally-pipelined/src/ifu/gsharePredictor.sv
View File

@ -30,35 +30,35 @@
module gsharePredictor module gsharePredictor
#(parameter int k = 10 #(parameter int k = 10
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
output logic [1:0] BPPredF, output logic [1:0] BPPredF,
// update // update
input logic [4:0] InstrClassE, input logic [4:0] InstrClassE,
input logic [4:0] BPInstrClassE, input logic [4:0] BPInstrClassE,
input logic [4:0] BPInstrClassD, input logic [4:0] BPInstrClassD,
input logic [4:0] BPInstrClassF, input logic [4:0] BPInstrClassF,
input logic BPPredDirWrongE, input logic BPPredDirWrongE,
input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCE,
input logic PCSrcE, input logic PCSrcE,
input logic [1:0] UpdateBPPredE input logic [1:0] UpdateBPPredE
); );
logic [k+1:0] GHR, GHRNext; logic [k+1:0] GHR, GHRNext;
logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
logic PHTUpdateEN; logic PHTUpdateEN;
logic BPClassWrongNonCFI; logic BPClassWrongNonCFI;
logic BPClassWrongCFI; logic BPClassWrongCFI;
logic BPClassRightNonCFI; logic BPClassRightNonCFI;
logic BPClassRightBPWrong; logic BPClassRightBPWrong;
logic BPClassRightBPRight; logic BPClassRightBPRight;
logic [6:0] GHRMuxSel; logic [6:0] GHRMuxSel;
logic GHRUpdateEN; logic GHRUpdateEN;
logic [k-1:0] GHRLookup; logic [k-1:0] GHRLookup;
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@ -92,10 +92,10 @@ module gsharePredictor
end end
flopenr #(k+2) GlobalHistoryRegister(.clk(clk), flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
.reset(reset), .reset(reset),
.en((GHRUpdateEN)), .en((GHRUpdateEN)),
.d(GHRNext), .d(GHRNext),
.q(GHR)); .q(GHR));
// if actively updating the GHR at the time of prediction we want to us // if actively updating the GHR at the time of prediction we want to us
// GHRNext as the lookup rather than GHR. // GHRNext as the lookup rather than GHR.
@ -109,14 +109,14 @@ module gsharePredictor
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
SRAM2P1R1W #(k, 2) PHT(.clk(clk), SRAM2P1R1W #(k, 2) PHT(.clk(clk),
.reset(reset), .reset(reset),
//.RA1(GHR[k-1:0]), //.RA1(GHR[k-1:0]),
.RA1(GHRLookup ^ PCNextF[k:1]), .RA1(GHRLookup ^ PCNextF[k:1]),
.RD1(BPPredF), .RD1(BPPredF),
.REN1(~StallF), .REN1(~StallF),
.WA1(PHTUpdateAdr ^ PCE[k:1]), .WA1(PHTUpdateAdr ^ PCE[k:1]),
.WD1(UpdateBPPredE), .WD1(UpdateBPPredE),
.WEN1(PHTUpdateEN), .WEN1(PHTUpdateEN),
.BitWEN1(2'b11)); .BitWEN1(2'b11));
endmodule // gsharePredictor endmodule // gsharePredictor

214
wally-pipelined/src/ifu/ifu.sv
View File

@ -27,80 +27,80 @@
`include "wally-config.vh" `include "wally-config.vh"
module ifu ( module ifu (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushF, FlushD, FlushE, FlushM, FlushW, input logic FlushF, FlushD, FlushE, FlushM, FlushW,
// Fetch // Fetch
input logic [`XLEN-1:0] InstrInF, input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF, input logic InstrAckF,
output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] PCF,
output logic [`PA_BITS-1:0] InstrPAdrF, output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF, output logic InstrReadF,
output logic ICacheStallF, output logic ICacheStallF,
// Execute // Execute
output logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCLinkE,
input logic PCSrcE, input logic PCSrcE,
input logic [`XLEN-1:0] PCTargetE, input logic [`XLEN-1:0] PCTargetE,
output logic [`XLEN-1:0] PCE, output logic [`XLEN-1:0] PCE,
output logic BPPredWrongE, output logic BPPredWrongE,
// Mem // Mem
input logic RetM, TrapM, input logic RetM, TrapM,
input logic [`XLEN-1:0] PrivilegedNextPCM, input logic [`XLEN-1:0] PrivilegedNextPCM,
input logic InvalidateICacheM, input logic InvalidateICacheM,
output logic [31:0] InstrD, InstrM, output logic [31:0] InstrD, InstrM,
output logic [`XLEN-1:0] PCM, output logic [`XLEN-1:0] PCM,
output logic [4:0] InstrClassM, output logic [4:0] InstrClassM,
output logic BPPredDirWrongM, output logic BPPredDirWrongM,
output logic BTBPredPCWrongM, output logic BTBPredPCWrongM,
output logic RASPredPCWrongM, output logic RASPredPCWrongM,
output logic BPPredClassNonCFIWrongM, output logic BPPredClassNonCFIWrongM,
// Writeback // Writeback
// output logic [`XLEN-1:0] PCLinkW, // output logic [`XLEN-1:0] PCLinkW,
// Faults // Faults
input logic IllegalBaseInstrFaultD, input logic IllegalBaseInstrFaultD,
output logic ITLBInstrPageFaultF, output logic ITLBInstrPageFaultF,
output logic IllegalIEUInstrFaultD, output logic IllegalIEUInstrFaultD,
output logic InstrMisalignedFaultM, output logic InstrMisalignedFaultM,
output logic [`XLEN-1:0] InstrMisalignedAdrM, output logic [`XLEN-1:0] InstrMisalignedAdrM,
// mmu management // mmu management
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] PTE, input logic [`XLEN-1:0] PTE,
input logic [1:0] PageType, input logic [1:0] PageType,
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic ITLBWriteF, ITLBFlushF, input logic ITLBWriteF, ITLBFlushF,
input logic WalkerInstrPageFaultF, input logic WalkerInstrPageFaultF,
output logic ITLBMissF, output logic ITLBMissF,
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic InstrAccessFaultF output logic InstrAccessFaultF
); );
logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic PrivilegedChangePCM; logic PrivilegedChangePCM;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
logic [`XLEN-3:0] PCPlusUpperF; logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF; logic CompressedF;
logic [31:0] InstrRawD, FinalInstrRawF; logic [31:0] InstrRawD, FinalInstrRawF;
logic [31:0] InstrE; logic [31:0] InstrE;
logic [`XLEN-1:0] PCD; logic [`XLEN-1:0] PCD;
localparam [31:0] nop = 32'h00000013; // instruction for NOP localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic reset_q; // *** look at this later. logic reset_q; // *** look at this later.
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
logic [`XLEN+1:0] PCFExt; logic [`XLEN+1:0] PCFExt;
generate generate
if (`XLEN==32) begin if (`XLEN==32) begin
@ -138,9 +138,9 @@ module ifu (
// branch predictor signals // branch predictor signals
logic SelBPPredF; logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F; logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
logic [4:0] InstrClassD, InstrClassE; logic [4:0] InstrClassD, InstrClassE;
// *** put memory interface on here, InstrF becomes output // *** put memory interface on here, InstrF becomes output
@ -149,10 +149,10 @@ module ifu (
// assign InstrReadF = 1; // *** & ICacheMissF; add later // assign InstrReadF = 1; // *** & ICacheMissF; add later
icache icache(.*, icache icache(.*,
.PCNextF(PCNextFPhys), .PCNextF(PCNextFPhys),
.PCPF(PCPFmmu), .PCPF(PCPFmmu),
.WalkerInstrPageFaultF, .WalkerInstrPageFaultF,
.InvalidateICacheM); .InvalidateICacheM);
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD); flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
@ -160,33 +160,33 @@ module ifu (
assign PrivilegedChangePCM = RetM | TrapM; assign PrivilegedChangePCM = RetM | TrapM;
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
.d1(BPPredPCF), .d1(BPPredPCF),
.s(SelBPPredF), .s(SelBPPredF),
.y(PCNext0F)); .y(PCNext0F));
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), mux2 #(`XLEN) pcmux1(.d0(PCNext0F),
.d1(PCCorrectE), .d1(PCCorrectE),
.s(BPPredWrongE), .s(BPPredWrongE),
.y(PCNext1F)); .y(PCNext1F));
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
.d1(PCE), .d1(PCE),
.s(InvalidateICacheM), .s(InvalidateICacheM),
.y(PCNext2F)); .y(PCNext2F));
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
.d1(PrivilegedNextPCM), .d1(PrivilegedNextPCM),
.s(PrivilegedChangePCM), .s(PrivilegedChangePCM),
.y(PCNext3F)); .y(PCNext3F));
mux2 #(`XLEN) pcmux4(.d0(PCNext3F), mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
.d1(`RESET_VECTOR), .d1(`RESET_VECTOR),
.s(reset_q), .s(reset_q),
.y(UnalignedPCNextF)); .y(UnalignedPCNextF));
flop #(1) resetReg (.clk(clk), flop #(1) resetReg (.clk(clk),
.d(reset), .d(reset),
.q(reset_q)); .q(reset_q));
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
@ -197,20 +197,20 @@ module ifu (
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1) begin : bpred
// I am making the port connection explicit for now as I want to see them and they will be changing. // I am making the port connection explicit for now as I want to see them and they will be changing.
bpred bpred(.*, bpred bpred(.*,
.PCNextF(PCNextF), .PCNextF(PCNextF),
.BPPredPCF(BPPredPCF), .BPPredPCF(BPPredPCF),
.SelBPPredF(SelBPPredF), .SelBPPredF(SelBPPredF),
.PCE(PCE), .PCE(PCE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.PCTargetE(PCTargetE), .PCTargetE(PCTargetE),
.PCD(PCD), .PCD(PCD),
.PCLinkE(PCLinkE), .PCLinkE(PCLinkE),
.InstrClassE(InstrClassE), .InstrClassE(InstrClassE),
.BPPredWrongE(BPPredWrongE), .BPPredWrongE(BPPredWrongE),
.BPPredDirWrongE(BPPredDirWrongE), .BPPredDirWrongE(BPPredDirWrongE),
.BTBPredPCWrongE(BTBPredPCWrongE), .BTBPredPCWrongE(BTBPredPCWrongE),
.RASPredPCWrongE(RASPredPCWrongE), .RASPredPCWrongE(RASPredPCWrongE),
.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE)); .BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
end else begin : bpred end else begin : bpred
assign BPPredPCF = {`XLEN{1'b0}}; assign BPPredPCF = {`XLEN{1'b0}};
assign SelBPPredF = 1'b0; assign SelBPPredF = 1'b0;
@ -274,25 +274,25 @@ module ifu (
flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
flopenrc #(5) InstrClassRegE(.clk(clk), flopenrc #(5) InstrClassRegE(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.clear(FlushE), .clear(FlushE),
.d(InstrClassD), .d(InstrClassD),
.q(InstrClassE)); .q(InstrClassE));
flopenrc #(5) InstrClassRegM(.clk(clk), flopenrc #(5) InstrClassRegM(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallM), .en(~StallM),
.clear(FlushM), .clear(FlushM),
.d(InstrClassE), .d(InstrClassE),
.q(InstrClassM)); .q(InstrClassM));
flopenrc #(4) BPPredWrongRegM(.clk(clk), flopenrc #(4) BPPredWrongRegM(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallM), .en(~StallM),
.clear(FlushM), .clear(FlushM),
.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}), .d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM})); .q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
// seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL. // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.
// either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or // either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or

72
wally-pipelined/src/ifu/localHistoryPredictor.sv
View File

@ -31,24 +31,24 @@ module localHistoryPredictor
#( parameter int m = 6, // 2^m = number of local history branches #( parameter int m = 6, // 2^m = number of local history branches
parameter int k = 10 // number of past branches stored parameter int k = 10 // number of past branches stored
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, FlushF, input logic StallF, StallE, FlushF,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction, output logic [1:0] Prediction,
// update // update
input logic [`XLEN-1:0] UpdatePC, input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, PCSrcE, input logic UpdateEN, PCSrcE,
input logic [1:0] UpdatePrediction input logic [1:0] UpdatePrediction
); );
logic [2**m-1:0][k-1:0] LHRNextF; logic [2**m-1:0] [k-1:0] LHRNextF;
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;
logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF; logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
logic [1:0] UpdatePredictionF; logic [1:0] UpdatePredictionF;
assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; assign LHRFNext = {PCSrcE, LHRF[k-1:1]};
assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]}; assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
@ -65,15 +65,15 @@ module localHistoryPredictor
// .WEN1(UpdateEN), // .WEN1(UpdateEN),
// .BitWEN1(2'b11)); // .BitWEN1(2'b11));
genvar index; genvar index;
generate generate
for (index = 0; index < 2**m; index = index +1) begin:localhist for (index = 0; index < 2**m; index = index +1) begin:localhist
flopenr #(k) LocalHistoryRegister(.clk(clk), flopenr #(k) LocalHistoryRegister(.clk(clk),
.reset(reset), .reset(reset),
.en(UpdateEN && (index == UpdatePCIndex)), .en(UpdateEN && (index == UpdatePCIndex)),
.d(LHRFNext), .d(LHRFNext),
.q(LHRNextF[index])); .q(LHRNextF[index]));
end end
endgenerate endgenerate
@ -86,14 +86,14 @@ module localHistoryPredictor
// LHR referes to the address that the past k branches points to in the prediction stage // LHR referes to the address that the past k branches points to in the prediction stage
// LHRE refers to the address that the past k branches points to in the exectution stage // LHRE refers to the address that the past k branches points to in the exectution stage
SRAM2P1R1W #(k, 2) PHT(.clk(clk), SRAM2P1R1W #(k, 2) PHT(.clk(clk),
.reset(reset), .reset(reset),
.RA1(ForwardLHRNext), .RA1(ForwardLHRNext),
.RD1(PredictionMemory), .RD1(PredictionMemory),
.REN1(~StallF), .REN1(~StallF),
.WA1(LHRFNext), .WA1(LHRFNext),
.WD1(UpdatePrediction), .WD1(UpdatePrediction),
.WEN1(UpdateEN), .WEN1(UpdateEN),
.BitWEN1(2'b11)); .BitWEN1(2'b11));
@ -102,24 +102,24 @@ module localHistoryPredictor
// register the update value and the forwarding signal into the Fetch stage // register the update value and the forwarding signal into the Fetch stage
// TODO: add stall logic *** // TODO: add stall logic ***
flopr #(1) DoForwardingReg(.clk(clk), flopr #(1) DoForwardingReg(.clk(clk),
.reset(reset), .reset(reset),
.d(DoForwardingPHT), .d(DoForwardingPHT),
.q(DoForwardingPHTF)); .q(DoForwardingPHTF));
flopr #(2) UpdatePredictionReg(.clk(clk), flopr #(2) UpdatePredictionReg(.clk(clk),
.reset(reset), .reset(reset),
.d(UpdatePrediction), .d(UpdatePrediction),
.q(UpdatePredictionF)); .q(UpdatePredictionF));
assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory; assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
//pipeline for LHR //pipeline for LHR
flopenrc #(k) LHRFReg(.clk(clk), flopenrc #(k) LHRFReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallF), .en(~StallF),
.clear(FlushF), .clear(FlushF),
.d(ForwardLHRNext), .d(ForwardLHRNext),
.q(LHRF)); .q(LHRF));
/* /*
flopenrc #(k) LHRDReg(.clk(clk), flopenrc #(k) LHRDReg(.clk(clk),
.reset(reset), .reset(reset),

20
wally-pipelined/src/ifu/satCounter2.sv
View File

@ -28,28 +28,28 @@
`include "wally-config.vh" `include "wally-config.vh"
module satCounter2 module satCounter2
(input logic BrDir, (input logic BrDir,
input logic [1:0] OldState, input logic [1:0] OldState,
output logic [1:0] NewState output logic [1:0] NewState
); );
always_comb begin always_comb begin
case(OldState) case(OldState)
2'b00: begin 2'b00: begin
if(BrDir) NewState = 2'b01; if(BrDir) NewState = 2'b01;
else NewState = 2'b00; else NewState = 2'b00;
end end
2'b01: begin 2'b01: begin
if(BrDir) NewState = 2'b10; if(BrDir) NewState = 2'b10;
else NewState = 2'b00; else NewState = 2'b00;
end end
2'b10: begin 2'b10: begin
if(BrDir) NewState = 2'b11; if(BrDir) NewState = 2'b11;
else NewState = 2'b01; else NewState = 2'b01;
end end
2'b11: begin 2'b11: begin
if(BrDir) NewState = 2'b11; if(BrDir) NewState = 2'b11;
else NewState = 2'b10; else NewState = 2'b10;
end end
endcase endcase
end end

48
wally-pipelined/src/ifu/twoBitPredictor.sv
View File

@ -30,21 +30,21 @@
module twoBitPredictor module twoBitPredictor
#(parameter int Depth = 10 #(parameter int Depth = 10
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, input logic StallF,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction, output logic [1:0] Prediction,
// update // update
input logic [`XLEN-1:0] UpdatePC, input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, input logic UpdateEN,
input logic [1:0] UpdatePrediction input logic [1:0] UpdatePrediction
); );
logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex; logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;
logic DoForwarding, DoForwardingF; logic DoForwarding, DoForwardingF;
logic [1:0] UpdatePredictionF; logic [1:0] UpdatePredictionF;
// hashing function for indexing the PC // hashing function for indexing the PC
@ -56,14 +56,14 @@ module twoBitPredictor
SRAM2P1R1W #(Depth, 2) PHT(.clk(clk), SRAM2P1R1W #(Depth, 2) PHT(.clk(clk),
.reset(reset), .reset(reset),
.RA1(LookUpPCIndex), .RA1(LookUpPCIndex),
.RD1(PredictionMemory), .RD1(PredictionMemory),
.REN1(~StallF), .REN1(~StallF),
.WA1(UpdatePCIndex), .WA1(UpdatePCIndex),
.WD1(UpdatePrediction), .WD1(UpdatePrediction),
.WEN1(UpdateEN), .WEN1(UpdateEN),
.BitWEN1(2'b11)); .BitWEN1(2'b11));
// need to forward when updating to the same address as reading. // need to forward when updating to the same address as reading.
// first we compare to see if the update and lookup addreses are the same // first we compare to see if the update and lookup addreses are the same
@ -71,14 +71,14 @@ module twoBitPredictor
// register the update value and the forwarding signal into the Fetch stage // register the update value and the forwarding signal into the Fetch stage
flopr #(1) DoForwardingReg(.clk(clk), flopr #(1) DoForwardingReg(.clk(clk),
.reset(reset), .reset(reset),
.d(DoForwarding), .d(DoForwarding),
.q(DoForwardingF)); .q(DoForwardingF));
flopr #(2) UpdatePredictionReg(.clk(clk), flopr #(2) UpdatePredictionReg(.clk(clk),
.reset(reset), .reset(reset),
.d(UpdatePrediction), .d(UpdatePrediction),
.q(UpdatePredictionF)); .q(UpdatePredictionF));
assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory; assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;

27
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -154,9 +154,30 @@ module wallypipelinedhart (
logic BreakpointFaultM, EcallFaultM; logic BreakpointFaultM, EcallFaultM;
ifu ifu(.InstrInF(InstrRData), ifu ifu(
.WalkerInstrPageFaultF(WalkerInstrPageFaultF), .clk, .reset,
.*); // instruction fetch unit: PC, branch prediction, instruction cache .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF,
.PCLinkE, .PCSrcE, .PCTargetE, .PCE,
.BPPredWrongE,
.RetM, .TrapM,
.PrivilegedNextPCM, .InvalidateICacheM,
.InstrD, .InstrM,
.PCM, .InstrClassM,
.BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
.InstrMisalignedFaultM, .InstrMisalignedAdrM,
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.ITLBWriteF, .ITLBFlushF,
.WalkerInstrPageFaultF,
.ITLBMissF,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.InstrAccessFaultF
); // instruction fetch unit: PC, branch prediction, instruction cache
ieu ieu(.*); // integer execution unit: integer register file, datapath and controller ieu ieu(.*); // integer execution unit: integer register file, datapath and controller

1
wally-pipelined/testbench/testbench.sv
View File

@ -101,6 +101,7 @@ logic [3:0] dummy;
"arch32priv": tests = arch32priv; "arch32priv": tests = arch32priv;
"arch32c": if (`C_SUPPORTED) tests = arch32c; "arch32c": if (`C_SUPPORTED) tests = arch32c;
"arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
"imperas32p": tests = imperas32p; "imperas32p": tests = imperas32p;
"imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;

297
wally-pipelined/testbench/tests.vh
View File

@ -668,158 +668,157 @@ string imperas32f[] = '{
"rv32i_m/M/remu-01", "5010" "rv32i_m/M/remu-01", "5010"
}; };
/*
string arch32f[] = '{ string arch32f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/M/div-01", "5010", // "rv32i_m/F/fadd_b1-01", "7220",
"fadd_b1-01", "", // "rv32i_m/F/fadd_b10-01", "2270",
"fadd_b10-01", "", // "rv32i_m/F/fadd_b11-01", "3fb40",
"fadd_b11-01", "", // "rv32i_m/F/fadd_b12-01", "21b0",
"fadd_b12-01", "", // "rv32i_m/F/fadd_b13-01", "3660",
"fadd_b13-01", "", // "rv32i_m/F/fadd_b2-01", "38b0",
"fadd_b2-01", "", // "rv32i_m/F/fadd_b3-01", "b320",
"fadd_b3-01", "", // "rv32i_m/F/fadd_b4-01", "3480",
"fadd_b4-01", "", // "rv32i_m/F/fadd_b5-01", "3700",
"fadd_b5-01", "", // "rv32i_m/F/fadd_b7-01", "3520",
"fadd_b7-01", "", // "rv32i_m/F/fadd_b8-01", "104a0",
"fadd_b8-01", "", "rv32i_m/F/fclass_b1-01", "2090",
"fclass_b1-01", "", "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
"fcvt.s.w_b25-01", "", "rv32i_m/F/fcvt.s.w_b26-01", "3290",
"fcvt.s.w_b26-01", "", "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
"fcvt.s.wu_b25-01", "", "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
"fcvt.s.wu_b26-01", "", // "rv32i_m/F/fcvt.w.s_b1-01", "2090",
"fcvt.w.s_b1-01", "", // "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
"fcvt.w.s_b22-01", "", // "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
"fcvt.w.s_b23-01", "", // "rv32i_m/F/fcvt.w.s_b24-01", "21b0",
"fcvt.w.s_b24-01", "", // "rv32i_m/F/fcvt.w.s_b27-01", "2090",
"fcvt.w.s_b27-01", "", // "rv32i_m/F/fcvt.w.s_b28-01", "2090",
"fcvt.w.s_b28-01", "", // "rv32i_m/F/fcvt.w.s_b29-01", "2150",
"fcvt.w.s_b29-01", "", // "rv32i_m/F/fcvt.wu.s_b1-01", "2090",
"fcvt.wu.s_b1-01", "", // "rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
"fcvt.wu.s_b22-01", "", // "rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
"fcvt.wu.s_b23-01", "", // "rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
"fcvt.wu.s_b24-01", "", // "rv32i_m/F/fcvt.wu.s_b27-01", "2090",
"fcvt.wu.s_b27-01", "", // "rv32i_m/F/fcvt.wu.s_b28-01", "2090",
"fcvt.wu.s_b28-01", "", // "rv32i_m/F/fcvt.wu.s_b29-01", "2150",
"fcvt.wu.s_b29-01", "", // "rv32i_m/F/fdiv_b1-01", "7220",
"fdiv_b1-01", "", // "rv32i_m/F/fdiv_b2-01", "2350",
"fdiv_b2-01", "", // "rv32i_m/F/fdiv_b20-01", "38c0",
"fdiv_b20-01", "", // "rv32i_m/F/fdiv_b21-01", "7540",
"fdiv_b21-01", "", // "rv32i_m/F/fdiv_b3-01", "b320",
"fdiv_b3-01", "", // "rv32i_m/F/fdiv_b4-01", "3480",
"fdiv_b4-01", "", // "rv32i_m/F/fdiv_b5-01", "3700",
"fdiv_b5-01", "", // "rv32i_m/F/fdiv_b6-01", "3480",
"fdiv_b6-01", "", // "rv32i_m/F/fdiv_b7-01", "3520",
"fdiv_b7-01", "", // "rv32i_m/F/fdiv_b8-01", "104a0",
"fdiv_b8-01", "", // "rv32i_m/F/fdiv_b9-01", "d960",
"fdiv_b9-01", "", // "rv32i_m/F/feq_b1-01", "6220",
"feq_b1-01", "", // "rv32i_m/F/feq_b19-01", "a190",
"feq_b19-01", "", // "rv32i_m/F/fle_b1-01", "6220",
"fle_b1-01", "", // "rv32i_m/F/fle_b19-01", "a190",
"fle_b19-01", "", // "rv32i_m/F/flt_b1-01", "6220",
"flt_b1-01", "", // "rv32i_m/F/flt_b19-01", "8ee0",
"flt_b19-01", "", "rv32i_m/F/flw-align-01", "2010",
"flw-align-01", "", // "rv32i_m/F/fmadd_b1-01", "96860",
"fmadd_b1-01", "", "rv32i_m/F/fmadd_b14-01", "23d0",
"fmadd_b14-01", "", //--passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30",
"fmadd_b15-01", "", "rv32i_m/F/fmadd_b16-01", "39d0",
"fmadd_b16-01", "", "rv32i_m/F/fmadd_b17-01", "39d0",
"fmadd_b17-01", "", // "rv32i_m/F/fmadd_b18-01", "4d10",
"fmadd_b18-01", "", "rv32i_m/F/fmadd_b2-01", "4d60",
"fmadd_b2-01", "", "rv32i_m/F/fmadd_b3-01", "d4f0",
"fmadd_b3-01", "", "rv32i_m/F/fmadd_b4-01", "3700",
"fmadd_b4-01", "", "rv32i_m/F/fmadd_b5-01", "3ac0",
"fmadd_b5-01", "", "rv32i_m/F/fmadd_b6-01", "3700",
"fmadd_b6-01", "", // "rv32i_m/F/fmadd_b7-01", "d7f0",
"fmadd_b7-01", "", // "rv32i_m/F/fmadd_b8-01", "13f30",
"fmadd_b8-01", "", // "rv32i_m/F/fmax_b1-01", "7220",
"fmax_b1-01", "", // "rv32i_m/F/fmax_b19-01", "9e00",
"fmax_b19-01", "", // "rv32i_m/F/fmin_b1-01", "7220",
"fmin_b1-01", "", // "rv32i_m/F/fmin_b19-01", "9f20",
"fmin_b19-01", "", "rv32i_m/F/fmsub_b1-01", "96860",
"fmsub_b1-01", "", "rv32i_m/F/fmsub_b14-01", "23d0",
"fmsub_b14-01", "", // "rv32i_m/F/fmsub_b15-01", "19bb30",
"fmsub_b15-01", "", "rv32i_m/F/fmsub_b16-01", "39d0",
"fmsub_b16-01", "", "rv32i_m/F/fmsub_b17-01", "39d0",
"fmsub_b17-01", "", "rv32i_m/F/fmsub_b18-01", "42d0",
"fmsub_b18-01", "", "rv32i_m/F/fmsub_b2-01", "4d60",
"fmsub_b2-01", "", "rv32i_m/F/fmsub_b3-01", "d4f0",
"fmsub_b3-01", "", "rv32i_m/F/fmsub_b4-01", "3700",
"fmsub_b4-01", "", "rv32i_m/F/fmsub_b5-01", "3ac0",
"fmsub_b5-01", "", "rv32i_m/F/fmsub_b6-01", "3700",
"fmsub_b6-01", "", "rv32i_m/F/fmsub_b7-01", "37f0",
"fmsub_b7-01", "", "rv32i_m/F/fmsub_b8-01", "13f30",
"fmsub_b8-01", "", "rv32i_m/F/fmul_b1-01", "7220",
"fmul_b1-01", "", "rv32i_m/F/fmul_b2-01", "38c0",
"fmul_b2-01", "", "rv32i_m/F/fmul_b3-01", "b320",
"fmul_b3-01", "", "rv32i_m/F/fmul_b4-01", "3480",
"fmul_b4-01", "", "rv32i_m/F/fmul_b5-01", "3700",
"fmul_b5-01", "", "rv32i_m/F/fmul_b6-01", "3480",
"fmul_b6-01", "", "rv32i_m/F/fmul_b7-01", "3520",
"fmul_b7-01", "", "rv32i_m/F/fmul_b8-01", "104a0",
"fmul_b8-01", "", "rv32i_m/F/fmul_b9-01", "d960",
"fmul_b9-01", "", "rv32i_m/F/fmv.w.x_b25-01", "2090",
"fmv.w.x_b25-01", "", "rv32i_m/F/fmv.w.x_b26-01", "2090",
"fmv.w.x_b26-01", "", "rv32i_m/F/fmv.x.w_b1-01", "2090",
"fmv.x.w_b1-01", "", "rv32i_m/F/fmv.x.w_b22-01", "2090",
"fmv.x.w_b22-01", "", "rv32i_m/F/fmv.x.w_b23-01", "2090",
"fmv.x.w_b23-01", "", "rv32i_m/F/fmv.x.w_b24-01", "2090",
"fmv.x.w_b24-01", "", "rv32i_m/F/fmv.x.w_b27-01", "2090",
"fmv.x.w_b27-01", "", "rv32i_m/F/fmv.x.w_b28-01", "2090",
"fmv.x.w_b28-01", "", "rv32i_m/F/fmv.x.w_b29-01", "2090",
"fmv.x.w_b29-01", "", "rv32i_m/F/fnmadd_b1-01", "96870",
"fnmadd_b1-01", "", "rv32i_m/F/fnmadd_b14-01", "23d0",
"fnmadd_b14-01", "", // timeconsuming "rv32i_m/F/fnmadd_b15-01", "19bb40",
"fnmadd_b15-01", "", "rv32i_m/F/fnmadd_b16-01", "39d0",
"fnmadd_b16-01", "", "rv32i_m/F/fnmadd_b17-01", "39d0",
"fnmadd_b17-01", "", "rv32i_m/F/fnmadd_b18-01", "4d10",
"fnmadd_b18-01", "", "rv32i_m/F/fnmadd_b2-01", "4d60",
"fnmadd_b2-01", "", "rv32i_m/F/fnmadd_b3-01", "d4f0",
"fnmadd_b3-01", "", "rv32i_m/F/fnmadd_b4-01", "3700",
"fnmadd_b4-01", "", "rv32i_m/F/fnmadd_b5-01", "3ac0",
"fnmadd_b5-01", "", "rv32i_m/F/fnmadd_b6-01", "3700",
"fnmadd_b6-01", "", "rv32i_m/F/fnmadd_b7-01", "37f0",
"fnmadd_b7-01", "", "rv32i_m/F/fnmadd_b8-01", "13f30",
"fnmadd_b8-01", "", "rv32i_m/F/fnmsub_b1-01", "96870",
"fnmsub_b1-01", "", "rv32i_m/F/fnmsub_b14-01", "23d0",
"fnmsub_b14-01", "", // timeconsuming "rv32i_m/F/fnmsub_b15-01", "19bb30",
"fnmsub_b15-01", "", "rv32i_m/F/fnmsub_b16-01", "39d0",
"fnmsub_b16-01", "", "rv32i_m/F/fnmsub_b17-01", "39d0",
"fnmsub_b17-01", "", "rv32i_m/F/fnmsub_b18-01", "4d10",
"fnmsub_b18-01", "", "rv32i_m/F/fnmsub_b2-01", "4d60",
"fnmsub_b2-01", "", "rv32i_m/F/fnmsub_b3-01", "4df0",
"fnmsub_b3-01", "", "rv32i_m/F/fnmsub_b4-01", "3700",
"fnmsub_b4-01", "", "rv32i_m/F/fnmsub_b5-01", "3ac0",
"fnmsub_b5-01", "", "rv32i_m/F/fnmsub_b6-01", "3700",
"fnmsub_b6-01", "", "rv32i_m/F/fnmsub_b7-01", "37f0",
"fnmsub_b7-01", "", "rv32i_m/F/fnmsub_b8-01", "13f30",
"fnmsub_b8-01", "", "rv32i_m/F/fsgnj_b1-01", "7220",
"fsgnj_b1-01", "", "rv32i_m/F/fsgnjn_b1-01", "7220",
"fsgnjn_b1-01", "", "rv32i_m/F/fsgnjx_b1-01", "7220",
"fsgnjx_b1-01", "", "rv32i_m/F/fsqrt_b1-01", "2090",
"fsqrt_b1-01", "", "rv32i_m/F/fsqrt_b2-01", "2090",
"fsqrt_b2-01", "", "rv32i_m/F/fsqrt_b20-01", "2090",
"fsqrt_b20-01", "", "rv32i_m/F/fsqrt_b3-01", "2090",
"fsqrt_b3-01", "", "rv32i_m/F/fsqrt_b4-01", "2090",
"fsqrt_b4-01", "", "rv32i_m/F/fsqrt_b5-01", "2090",
"fsqrt_b5-01", "", "rv32i_m/F/fsqrt_b7-01", "2090",
"fsqrt_b7-01", "", "rv32i_m/F/fsqrt_b8-01", "2090",
"fsqrt_b8-01", "", "rv32i_m/F/fsqrt_b9-01", "3310",
"fsqrt_b9-01", "", "rv32i_m/F/fsub_b1-01", "7220",
"fsub_b1-01", "", "rv32i_m/F/fsub_b10-01", "2250",
"fsub_b10-01", "", "rv32i_m/F/fsub_b11-01", "3fb40",
"fsub_b11-01", "", "rv32i_m/F/fsub_b12-01", "21b0",
"fsub_b12-01", "", "rv32i_m/F/fsub_b13-01", "3660",
"fsub_b13-01", "", "rv32i_m/F/fsub_b2-01", "38b0",
"fsub_b2-01", "", "rv32i_m/F/fsub_b3-01", "b320",
"fsub_b3-01", "", "rv32i_m/F/fsub_b4-01", "3480",
"fsub_b4-01", "", "rv32i_m/F/fsub_b5-01", "3700",
"fsub_b5-01", "", "rv32i_m/F/fsub_b7-01", "3520",
"fsub_b7-01", "", "rv32i_m/F/fsub_b8-01", "104a0",
"fsub_b8-01", "", "rv32i_m/F/fsw-align-01", "2010"
"fsw-align-01, ""
}; };
*/
string arch32c[] = '{ string arch32c[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,