Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

README.md

@@ -14,6 +14,8 @@ cd ../addins
 git clone https://github.com/riscv-non-isa/riscv-arch-test
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 cd riscv-isa-sim
+cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
+<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
 mkdir build
 cd build
 set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)

wally-pipelined/regression/regression-wally.py

@@ -48,6 +48,7 @@ for test in tests64:
         cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
+#tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 for test in tests32:
   tc = TestCase(

wally-pipelined/regression/sim-wally

@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32m"
+vsim -do "do wally-pipelined.do rv32g arch32f"
 

wally-pipelined/regression/sim-wally-batch

@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64g arch64m
+do wally-pipelined-batch.do rv32g arch32f
 !

wally-pipelined/regression/wave-dos/peripheral-waves.do

@@ -53,7 +53,7 @@ add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
 add wave -divider
 add wave -hex /testbench/PCW
 #add wave -hex /testbench/InstrW
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
+#add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
 #add wave /testbench/InstrWName
 add wave -hex /testbench/dut/hart/ReadDataW
 add wave -hex /testbench/dut/hart/ieu/dp/ResultW

wally-pipelined/src/cache/cachereplacementpolicy.sv

@@ -49,7 +49,7 @@ module cachereplacementpolicy
   logic 					LRUWriteEnD;
   
   /* verilator lint_off BLKLOOPINIT */
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) begin
       RAdrD <= '0;
       MemPAdrMD <= '0;

wally-pipelined/src/cache/cacheway.sv

@@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
     
   
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) 
   	ValidBits <= {NUMLINES{1'b0}};
     else if (InvalidateAll) 
@@ -134,14 +134,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   generate
     if(DIRTY_BITS) begin
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};
 	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
 	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
       end
 
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	SetDirtyD <= SetDirty;
 	ClearDirtyD <= ClearDirty;
       end

wally-pipelined/src/cache/dcachefsm.sv

@@ -144,7 +144,7 @@ module dcachefsm
   assign CntEn = PreCntEn & AHBAck;
 
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;  
   

wally-pipelined/src/cache/icachefsm.sv

@@ -116,7 +116,7 @@ module icachefsm
   logic 		       PreCntEn;
 
   // the FSM is always runing, do not stall.
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;
 

wally-pipelined/src/fpu/fpu.sv

@@ -41,7 +41,7 @@ module fpu (
   output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
   output logic 		   FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
   output logic 		   IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
-  output logic [4:0] 	   SetFflagsM        // FMA flags (to privileged unit)
+  output logic [4:0] 	   SetFflagsM        // FPU flags (to privileged unit)
   );
 
   //*** make everything FLEN at some point
@@ -267,7 +267,7 @@ module fpu (
      // BEGIN MEMORY STAGE
      
      // FPU flag selection - to privileged
-     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM);
+     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
   
      // M/W pipe registers
      flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 

wally-pipelined/src/ifu/CodeAligner.py

@@ -0,0 +1,98 @@
+import os
+
+# Kevin Wan kewan@hmc.edu 10/27/2021
+def read_input(filename):  #1
+    """Takes in a string filename and outputs the parsed verilog code by line into a list
+    such that each element of the list is one line of verilog code as a string."""
+    lineOfCode = []
+    input_file = open(filename, 'r')
+    for line in input_file:
+        lineOfCode.append(line)
+    return lineOfCode
+###################################################################################
+def ID_start(GiantString):#2
+    """takes in the list of sv file lines, outputs the location that variable names should start"""
+    VarLoc = 0 
+    VarLineNum = None
+    for lines in GiantString:
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines:# need to account for these space
+                NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear. 
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines) # Update this number if new record is made. 
+            else:   
+                NowLoc = lines.find('logic') + 7 # same as before.
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines)
+    #print("Furthest variable appears on line", VarLineNum + 1,VarLoc)   # Disable this line after debugging. 
+    return VarLoc
+##################################################################################
+def modified_logNew(GS,SOV): #3
+    Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it. 
+    Out = []
+    for l in GS:
+        lines = l.replace('\t',' ')
+
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines: # the line is an extended declaration. 
+                EditLoc = lines.find("]") # Re-finds the string index number of ]. 
+                VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1  # Checks where variable declaration currently is at. 
+                #print(VarLoc,lines[VarLoc])# VERIFIED
+                NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind) 
+                Out.append(NewLine)# Verified0957 10272021
+            else:
+                EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
+
+                VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
+                NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
+
+                Out.append(NewLine1)# Verified 1005 10272021
+        else:
+            Out.append(lines)
+    return Out   
+################################################################################
+def write_to_output(filename,GiantString,OW=True,Lines_editted=None):   #4
+ """Filename is preferrably passed from the early function calls"""
+ """GiantString has all the corrected features in the code, each line is a good verilog code line"""
+ newname = filename
+ if not OW or OW =='f':   #which means no overwrite (create a new file)
+  Decomposed=filename.split('.')
+  newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned. 
+  
+ OutFile = open(newname,'w') # This step should create a new file. 
+ OutFile.writelines(GiantString)
+ OutFile.close()
+ print("Success! " + newname + " Now contains an aligned file!")
+ return newname
+#################################################################################
+
+def FindCharRel(Ln):
+    #returns the computer location of a character's first occurence
+    for num in range(len(Ln)):
+        if Ln[num] != " ":
+            return num 
+
+
+def Mod_Space_at(Ln,loc,diff):
+    #loc is the varLoc from mln, diff is varLoc - Ind
+    if diff > 0: # to delete
+        NewString = Ln[:(loc-diff)] + Ln[loc:]
+        
+    if diff < 0: # to add
+        NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
+    if diff == 0:
+        NewString = Ln
+    
+    return NewString
+
+def main_filehandler(overwrite=False):
+    for filename in os.listdir():
+        if ".py" not in filename:
+            GiantString = read_input(filename)
+            SOV = ID_start(GiantString)
+            ModifiedGS = modified_logNew(GiantString,SOV)
+            Newname = write_to_output(filename,ModifiedGS,overwrite)
+ 
+main_filehandler(True)

wally-pipelined/src/ifu/RAsPredictor.sv

@@ -62,7 +62,7 @@ module RASPredictor
       .q(PtrQ));
 
   // RAS must be reset. 
-  always_ff @ (posedge clk, posedge reset) begin
+  always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
  memory[index] <= {`XLEN{1'b0}};

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -154,9 +154,30 @@ module wallypipelinedhart (
   logic 		    BreakpointFaultM, EcallFaultM;
 
   
-  ifu ifu(.InstrInF(InstrRData),
+  ifu ifu(
-	  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+    .clk, .reset, 
-	  .*); // instruction fetch unit: PC, branch prediction, instruction cache
+    .StallF, .StallD, .StallE, .StallM, .StallW, 
+    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, 
+    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, 
+    .PCLinkE, .PCSrcE, .PCTargetE, .PCE,
+    .BPPredWrongE, 
+    .RetM, .TrapM, 
+    .PrivilegedNextPCM, .InvalidateICacheM,
+    .InstrD, .InstrM, 
+    .PCM, .InstrClassM, 
+    .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+    .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
+    .InstrMisalignedFaultM, .InstrMisalignedAdrM,
+    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
+    .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+    .ITLBWriteF, .ITLBFlushF,
+    .WalkerInstrPageFaultF,
+    .ITLBMissF,
+    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+    .InstrAccessFaultF
+	  
+	  ); // instruction fetch unit: PC, branch prediction, instruction cache
+    
 
   ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
 

wally-pipelined/testbench/testbench.sv

@@ -101,6 +101,7 @@ logic [3:0] dummy;
         "arch32priv":                     tests = arch32priv;
         "arch32c":      if (`C_SUPPORTED) tests = arch32c;
         "arch32m":      if (`M_SUPPORTED) tests = arch32m;
+        "arch32f":      if (`F_SUPPORTED) tests = arch32f;
         "imperas32i":                     tests = imperas32i;
         "imperas32p":                     tests = imperas32p;
         "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;

wally-pipelined/testbench/tests.vh

@@ -668,158 +668,157 @@ string imperas32f[] = '{
     "rv32i_m/M/remu-01", "5010"
    };
 
-/*
   string arch32f[] = '{
+
     `RISCVARCHTEST,
-    "rv32i_m/M/div-01", "5010",
+    // "rv32i_m/F/fadd_b1-01", "7220",
-    "fadd_b1-01", "",
+    // "rv32i_m/F/fadd_b10-01", "2270", 
-    "fadd_b10-01", "",
+    // "rv32i_m/F/fadd_b11-01", "3fb40",
-    "fadd_b11-01", "",
+    // "rv32i_m/F/fadd_b12-01", "21b0",
-    "fadd_b12-01", "",
+    // "rv32i_m/F/fadd_b13-01", "3660",
-    "fadd_b13-01", "",
+    // "rv32i_m/F/fadd_b2-01", "38b0",
-    "fadd_b2-01", "",
+    // "rv32i_m/F/fadd_b3-01", "b320",
-    "fadd_b3-01", "",
+    // "rv32i_m/F/fadd_b4-01", "3480",
-    "fadd_b4-01", "",
+    // "rv32i_m/F/fadd_b5-01", "3700",
-    "fadd_b5-01", "",
+    // "rv32i_m/F/fadd_b7-01", "3520",
-    "fadd_b7-01", "",
+    // "rv32i_m/F/fadd_b8-01", "104a0",
-    "fadd_b8-01", "",
+    "rv32i_m/F/fclass_b1-01", "2090",
-    "fclass_b1-01", "",
+    "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
-    "fcvt.s.w_b25-01", "",
+    "rv32i_m/F/fcvt.s.w_b26-01", "3290",
-    "fcvt.s.w_b26-01", "",
+    "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
-    "fcvt.s.wu_b25-01", "",
+    "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
-    "fcvt.s.wu_b26-01", "",
+//    "rv32i_m/F/fcvt.w.s_b1-01", "2090",
-    "fcvt.w.s_b1-01", "",
+//    "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
-    "fcvt.w.s_b22-01", "",
+    // "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
-    "fcvt.w.s_b23-01", "",
+    // "rv32i_m/F/fcvt.w.s_b24-01", "21b0",
-    "fcvt.w.s_b24-01", "",
+    // "rv32i_m/F/fcvt.w.s_b27-01", "2090",
-    "fcvt.w.s_b27-01", "",
+    // "rv32i_m/F/fcvt.w.s_b28-01", "2090",
-    "fcvt.w.s_b28-01", "",
+    // "rv32i_m/F/fcvt.w.s_b29-01", "2150",
-    "fcvt.w.s_b29-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b1-01", "2090",
-    "fcvt.wu.s_b1-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
-    "fcvt.wu.s_b22-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
-    "fcvt.wu.s_b23-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
-    "fcvt.wu.s_b24-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b27-01", "2090",
-    "fcvt.wu.s_b27-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b28-01", "2090",
-    "fcvt.wu.s_b28-01", "",
+    // "rv32i_m/F/fcvt.wu.s_b29-01", "2150",
-    "fcvt.wu.s_b29-01", "",
+    // "rv32i_m/F/fdiv_b1-01", "7220",
-    "fdiv_b1-01", "",
+    // "rv32i_m/F/fdiv_b2-01", "2350",
-    "fdiv_b2-01", "",
+    // "rv32i_m/F/fdiv_b20-01", "38c0",
-    "fdiv_b20-01", "",
+    // "rv32i_m/F/fdiv_b21-01", "7540",
-    "fdiv_b21-01", "",
+    // "rv32i_m/F/fdiv_b3-01", "b320",
-    "fdiv_b3-01", "",
+    // "rv32i_m/F/fdiv_b4-01", "3480",
-    "fdiv_b4-01", "",
+    // "rv32i_m/F/fdiv_b5-01", "3700",
-    "fdiv_b5-01", "",
+    // "rv32i_m/F/fdiv_b6-01", "3480",
-    "fdiv_b6-01", "",
+    // "rv32i_m/F/fdiv_b7-01", "3520",
-    "fdiv_b7-01", "",
+    // "rv32i_m/F/fdiv_b8-01", "104a0",
-    "fdiv_b8-01", "",
+    // "rv32i_m/F/fdiv_b9-01", "d960",
-    "fdiv_b9-01", "",
+    // "rv32i_m/F/feq_b1-01", "6220",
-    "feq_b1-01", "",
+    // "rv32i_m/F/feq_b19-01", "a190",
-    "feq_b19-01", "",
+    // "rv32i_m/F/fle_b1-01", "6220",
-    "fle_b1-01", "",
+    // "rv32i_m/F/fle_b19-01", "a190",
-    "fle_b19-01", "",
+    // "rv32i_m/F/flt_b1-01", "6220",
-    "flt_b1-01", "",
+    // "rv32i_m/F/flt_b19-01", "8ee0",
-    "flt_b19-01", "",
+    "rv32i_m/F/flw-align-01", "2010",
-    "flw-align-01", "",
+//    "rv32i_m/F/fmadd_b1-01", "96860",
-    "fmadd_b1-01", "",
+    "rv32i_m/F/fmadd_b14-01", "23d0",
-    "fmadd_b14-01", "",
+//--passes but is timeconsuming    "rv32i_m/F/fmadd_b15-01", "19bb30",
-    "fmadd_b15-01", "",
+    "rv32i_m/F/fmadd_b16-01", "39d0",
-    "fmadd_b16-01", "",
+    "rv32i_m/F/fmadd_b17-01", "39d0",
-    "fmadd_b17-01", "",
+//    "rv32i_m/F/fmadd_b18-01", "4d10",
-    "fmadd_b18-01", "",
+    "rv32i_m/F/fmadd_b2-01", "4d60",
-    "fmadd_b2-01", "",
+    "rv32i_m/F/fmadd_b3-01", "d4f0",
-    "fmadd_b3-01", "",
+    "rv32i_m/F/fmadd_b4-01", "3700",
-    "fmadd_b4-01", "",
+    "rv32i_m/F/fmadd_b5-01", "3ac0",
-    "fmadd_b5-01", "",
+    "rv32i_m/F/fmadd_b6-01", "3700",
-    "fmadd_b6-01", "",
+//    "rv32i_m/F/fmadd_b7-01", "d7f0",
-    "fmadd_b7-01", "",
+//    "rv32i_m/F/fmadd_b8-01", "13f30",
-    "fmadd_b8-01", "",
+    // "rv32i_m/F/fmax_b1-01", "7220",
-    "fmax_b1-01", "",
+    // "rv32i_m/F/fmax_b19-01", "9e00",
-    "fmax_b19-01", "",
+    // "rv32i_m/F/fmin_b1-01", "7220",
-    "fmin_b1-01", "",
+    // "rv32i_m/F/fmin_b19-01", "9f20",
-    "fmin_b19-01", "",
+    "rv32i_m/F/fmsub_b1-01", "96860",
-    "fmsub_b1-01", "",
+    "rv32i_m/F/fmsub_b14-01", "23d0",
-    "fmsub_b14-01", "",
+//    "rv32i_m/F/fmsub_b15-01", "19bb30",
-    "fmsub_b15-01", "",
+    "rv32i_m/F/fmsub_b16-01", "39d0",
-    "fmsub_b16-01", "",
+    "rv32i_m/F/fmsub_b17-01", "39d0",
-    "fmsub_b17-01", "",
+    "rv32i_m/F/fmsub_b18-01", "42d0",
-    "fmsub_b18-01", "",
+    "rv32i_m/F/fmsub_b2-01", "4d60",
-    "fmsub_b2-01", "",
+    "rv32i_m/F/fmsub_b3-01", "d4f0",
-    "fmsub_b3-01", "",
+    "rv32i_m/F/fmsub_b4-01", "3700",
-    "fmsub_b4-01", "",
+    "rv32i_m/F/fmsub_b5-01", "3ac0",
-    "fmsub_b5-01", "",
+    "rv32i_m/F/fmsub_b6-01", "3700",
-    "fmsub_b6-01", "",
+    "rv32i_m/F/fmsub_b7-01", "37f0",
-    "fmsub_b7-01", "",
+    "rv32i_m/F/fmsub_b8-01", "13f30",
-    "fmsub_b8-01", "",
+    "rv32i_m/F/fmul_b1-01", "7220",
-    "fmul_b1-01", "",
+    "rv32i_m/F/fmul_b2-01", "38c0",
-    "fmul_b2-01", "",
+    "rv32i_m/F/fmul_b3-01", "b320",
-    "fmul_b3-01", "",
+    "rv32i_m/F/fmul_b4-01", "3480",
-    "fmul_b4-01", "",
+    "rv32i_m/F/fmul_b5-01", "3700",
-    "fmul_b5-01", "",
+    "rv32i_m/F/fmul_b6-01", "3480",
-    "fmul_b6-01", "",
+    "rv32i_m/F/fmul_b7-01", "3520",
-    "fmul_b7-01", "",
+    "rv32i_m/F/fmul_b8-01", "104a0",
-    "fmul_b8-01", "",
+    "rv32i_m/F/fmul_b9-01", "d960",
-    "fmul_b9-01", "",
+    "rv32i_m/F/fmv.w.x_b25-01", "2090",
-    "fmv.w.x_b25-01", "",
+    "rv32i_m/F/fmv.w.x_b26-01", "2090",
-    "fmv.w.x_b26-01", "",
+    "rv32i_m/F/fmv.x.w_b1-01", "2090",
-    "fmv.x.w_b1-01", "",
+    "rv32i_m/F/fmv.x.w_b22-01", "2090",
-    "fmv.x.w_b22-01", "",
+    "rv32i_m/F/fmv.x.w_b23-01", "2090",
-    "fmv.x.w_b23-01", "",
+    "rv32i_m/F/fmv.x.w_b24-01", "2090",
-    "fmv.x.w_b24-01", "",
+    "rv32i_m/F/fmv.x.w_b27-01", "2090",
-    "fmv.x.w_b27-01", "",
+    "rv32i_m/F/fmv.x.w_b28-01", "2090",
-    "fmv.x.w_b28-01", "",
+    "rv32i_m/F/fmv.x.w_b29-01", "2090",
-    "fmv.x.w_b29-01", "",
+    "rv32i_m/F/fnmadd_b1-01", "96870",
-    "fnmadd_b1-01", "",
+    "rv32i_m/F/fnmadd_b14-01", "23d0",
-    "fnmadd_b14-01", "",
+// timeconsuming    "rv32i_m/F/fnmadd_b15-01", "19bb40",
-    "fnmadd_b15-01", "",
+    "rv32i_m/F/fnmadd_b16-01", "39d0",
-    "fnmadd_b16-01", "",
+    "rv32i_m/F/fnmadd_b17-01", "39d0",
-    "fnmadd_b17-01", "",
+    "rv32i_m/F/fnmadd_b18-01", "4d10",
-    "fnmadd_b18-01", "",
+    "rv32i_m/F/fnmadd_b2-01", "4d60",
-    "fnmadd_b2-01", "",
+    "rv32i_m/F/fnmadd_b3-01", "d4f0",
-    "fnmadd_b3-01", "",
+    "rv32i_m/F/fnmadd_b4-01", "3700",
-    "fnmadd_b4-01", "",
+    "rv32i_m/F/fnmadd_b5-01", "3ac0",
-    "fnmadd_b5-01", "",
+    "rv32i_m/F/fnmadd_b6-01", "3700",
-    "fnmadd_b6-01", "",
+    "rv32i_m/F/fnmadd_b7-01", "37f0",
-    "fnmadd_b7-01", "",
+    "rv32i_m/F/fnmadd_b8-01", "13f30",
-    "fnmadd_b8-01", "",
+    "rv32i_m/F/fnmsub_b1-01", "96870",
-    "fnmsub_b1-01", "",
+    "rv32i_m/F/fnmsub_b14-01", "23d0",
-    "fnmsub_b14-01", "",
+// timeconsuming    "rv32i_m/F/fnmsub_b15-01", "19bb30",
-    "fnmsub_b15-01", "",
+    "rv32i_m/F/fnmsub_b16-01", "39d0",
-    "fnmsub_b16-01", "",
+    "rv32i_m/F/fnmsub_b17-01", "39d0",
-    "fnmsub_b17-01", "",
+    "rv32i_m/F/fnmsub_b18-01", "4d10",
-    "fnmsub_b18-01", "",
+    "rv32i_m/F/fnmsub_b2-01", "4d60",
-    "fnmsub_b2-01", "",
+    "rv32i_m/F/fnmsub_b3-01", "4df0",
-    "fnmsub_b3-01", "",
+    "rv32i_m/F/fnmsub_b4-01", "3700",
-    "fnmsub_b4-01", "",
+    "rv32i_m/F/fnmsub_b5-01", "3ac0",
-    "fnmsub_b5-01", "",
+    "rv32i_m/F/fnmsub_b6-01", "3700",
-    "fnmsub_b6-01", "",
+    "rv32i_m/F/fnmsub_b7-01", "37f0",
-    "fnmsub_b7-01", "",
+    "rv32i_m/F/fnmsub_b8-01", "13f30",
-    "fnmsub_b8-01", "",
+    "rv32i_m/F/fsgnj_b1-01", "7220",
-    "fsgnj_b1-01", "",
+    "rv32i_m/F/fsgnjn_b1-01", "7220",
-    "fsgnjn_b1-01", "",
+    "rv32i_m/F/fsgnjx_b1-01", "7220",
-    "fsgnjx_b1-01", "",
+    "rv32i_m/F/fsqrt_b1-01", "2090",
-    "fsqrt_b1-01", "",
+    "rv32i_m/F/fsqrt_b2-01", "2090",
-    "fsqrt_b2-01", "",
+    "rv32i_m/F/fsqrt_b20-01", "2090",
-    "fsqrt_b20-01", "",
+    "rv32i_m/F/fsqrt_b3-01", "2090",
-    "fsqrt_b3-01", "",
+    "rv32i_m/F/fsqrt_b4-01", "2090",
-    "fsqrt_b4-01", "",
+    "rv32i_m/F/fsqrt_b5-01", "2090",
-    "fsqrt_b5-01", "",
+    "rv32i_m/F/fsqrt_b7-01", "2090",
-    "fsqrt_b7-01", "",
+    "rv32i_m/F/fsqrt_b8-01", "2090",
-    "fsqrt_b8-01", "",
+    "rv32i_m/F/fsqrt_b9-01", "3310",
-    "fsqrt_b9-01", "",
+    "rv32i_m/F/fsub_b1-01", "7220",
-    "fsub_b1-01", "",
+    "rv32i_m/F/fsub_b10-01", "2250",
-    "fsub_b10-01", "",
+    "rv32i_m/F/fsub_b11-01", "3fb40",
-    "fsub_b11-01", "",
+    "rv32i_m/F/fsub_b12-01", "21b0",
-    "fsub_b12-01", "",
+    "rv32i_m/F/fsub_b13-01", "3660",
-    "fsub_b13-01", "",
+    "rv32i_m/F/fsub_b2-01", "38b0",
-    "fsub_b2-01", "",
+    "rv32i_m/F/fsub_b3-01", "b320",
-    "fsub_b3-01", "",
+    "rv32i_m/F/fsub_b4-01", "3480",
-    "fsub_b4-01", "",
+    "rv32i_m/F/fsub_b5-01", "3700",
-    "fsub_b5-01", "",
+    "rv32i_m/F/fsub_b7-01", "3520",
-    "fsub_b7-01", "",
+    "rv32i_m/F/fsub_b8-01", "104a0",
-    "fsub_b8-01", "",
+    "rv32i_m/F/fsw-align-01", "2010"
-    "fsw-align-01, ""
 };
-*/
+
 
   string arch32c[] = '{
     `RISCVARCHTEST,