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Removed D2 and D2b from radix2 stage

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This commit is contained in:
David Harris 2022-09-20 04:20:38 -07:00
parent c77ec2aa9c
commit 705a2bd97b
2 changed files with 2 additions and 2 deletions
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2
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -117,7 +117,7 @@ module fdivsqrtiter(
generate generate
for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations
if (`RADIX == 2) begin: stage if (`RADIX == 2) begin: stage
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtM,
.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .qn(qn[i])); .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .qn(qn[i]));
end else begin: stage end else begin: stage

2
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -33,7 +33,7 @@
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
module fdivsqrtstage2 ( module fdivsqrtstage2 (
input logic [`DIVN-2:0] D, input logic [`DIVN-2:0] D,
input logic [`DIVb+3:0] DBar, D2, DBar2, input logic [`DIVb+3:0] DBar,
input logic [`DIVb:0] U, UM, input logic [`DIVb:0] U, UM,
input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C, input logic [`DIVb+1:0] C,