Finished up testbench reformatting

This commit is contained in:
Limnanthes Serafini 2023-04-13 19:18:26 -07:00
parent 99cd913d75
commit 6fddc591b5

View File

@ -560,7 +560,8 @@ module testbench;
int file;
string LogFile;
logic resetD, resetEdge;
logic Enable, InvalDelayed;
logic Enable;
logic InvalDelayed, InvalEdge;
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
dut.core.ifu.immu.immu.pmachecker.Cacheable &