forked from Github_Repos/cvw
Finished up testbench reformatting
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@ -560,7 +560,8 @@ module testbench;
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int file;
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string LogFile;
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logic resetD, resetEdge;
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logic Enable, InvalDelayed;
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logic Enable;
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logic InvalDelayed, InvalEdge;
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assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
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dut.core.ifu.immu.immu.pmachecker.Cacheable &
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