Merge branch 'main' of github.com:davidharrishmc/riscv-wally

pipelined/src/generic/mem/ram2p1r1wb.sv

@@ -70,6 +70,12 @@ module ram2p1r1wb
 
   
   // SRAMs address busses are always registered first
+  // *** likely issued DH and RT 12/20/22
+  //   wrong enable for write port registers
+  //  prefer to code read like ram1p1rw
+  //  prefer not to have two-cycle write latency
+  //  will require branch predictor changes
+  
   flopenr #(DEPTH) RA1Reg(clk, reset, REN1, RA1, RA1Q);
   flopenr #(DEPTH) WA1Reg(clk, reset, REN1, WA1, WA1Q);
   flopr   #(1)     WEN1Reg(clk, reset, WEN1, WEN1Q);

pipelined/src/generic/mem/rom1p1r.sv

@@ -52,6 +52,7 @@ module rom1p1r
     if(ce) dout <= ROM[addr];    
   end
 
+  // for FPGA, initialize with zero-stage bootloader
   if(PRELOAD_ENABLED) begin
     initial begin
       ROM[0] =  64'h9581819300002197;