busybear: add 2nd dtim for bootram

wally-pipelined/config/busybear/wally-config.vh

@@ -61,16 +61,16 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define TIMBASE    64'h0000000080000000
+`define TIMBASE       32'h80000000
-`define TIMRANGE   64'h0000000007FFFFFF
+`define TIMRANGE      32'h07FFFFFF
-`define BOOTTIMBASE    64'h0000000000000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
+`define BOOTTIMBASE   32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
-`define BOOTTIMRANGE   64'h0000000000004000
+`define BOOTTIMRANGE  32'h00004000
-`define CLINTBASE  64'h0000000002000000
+`define CLINTBASE     32'h02000000
-`define CLINTRANGE 64'h000000000000BFFF
+`define CLINTRANGE    32'h0000BFFF
-//`define GPIOBASE   64'h0000000010012000 // no GPIO in linux for now
+//`define GPIOBASE    32'h10012000 // no GPIO in linux for now
-//`define GPIORANGE  64'h00000000000000FF
+//`define GPIORANGE   32'h000000FF
-`define UARTBASE   64'h0000000010000000
+`define UARTBASE      32'h10000000
-`define UARTRANGE  64'h0000000000000007
+`define UARTRANGE     32'h00000007
 // Bus Interface width
 `define AHBW 64
 

wally-pipelined/src/uncore/dtim.sv

@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module dtim (
+module dtim #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
   input  logic [1:0]       MemRWtim,
   input  logic [18:0]      HADDR, 
@@ -35,7 +35,8 @@ module dtim (
   output logic             HRESPTim, HREADYTim
 );
 
-  logic [`XLEN-1:0] RAM[0:65535];
+  //logic [`XLEN-1:0] RAM[0:65535];
+  logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE-BASE)>>1+(`XLEN/32)];
   logic [18:0] HWADDR;
   logic [`XLEN-1:0] HREADTim0;
 

wally-pipelined/src/uncore/uncore.sv

@@ -58,12 +58,12 @@ module uncore (
   );
   
   logic [`XLEN-1:0] HWDATA;
-  logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADGPIO, HREADUART;
+  logic [`XLEN-1:0] HREADBootTim, HREADTim, HREADCLINT, HREADGPIO, HREADUART;
   logic            HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
-  logic            HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
+  logic            HRESPBootTim, HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
-  logic            HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;  
+  logic            HREADYBootTim, HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;  
   logic [1:0]      MemRW;
-  logic [1:0]      MemRWtim, MemRWclint, MemRWgpio, MemRWuart;
+  logic [1:0]      MemRWboottim, MemRWtim, MemRWclint, MemRWgpio, MemRWuart;
   logic            UARTIntr;// *** will need to tie INTR to an interrupt handler
   
 
@@ -71,16 +71,17 @@ module uncore (
   adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
   adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
   adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
-  //Busybear: for now, leaving out gpio since OVPsim doesn't seem to have it
+  // Busybear: for now, leaving out gpio since OVPsim doesn't seem to have it
   //adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); 
   adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
   assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
   
   // Enable read or write based on decoded address
   assign MemRW = {~HWRITE, HWRITED};
+  assign MemRWboottim = MemRW & {2{HSELBootTim}};
   assign MemRWtim = MemRW & {2{HSELTim}};
   assign MemRWclint = MemRW & {2{HSELCLINT}};
-  assign MemRWgpio = MemRW & {2{HSELGPIO}};
+  //assign MemRWgpio = MemRW & {2{HSELGPIO}};
   assign MemRWuart = MemRW & {2{HSELUART}};
 /*  always_ff @(posedge HCLK) begin
     HADDRD <= HADDR;
@@ -94,11 +95,13 @@ module uncore (
   subwordwrite sww(.*);
 
   // tightly integrated memory
-  dtim dtim(.HADDR(HADDR[18:0]), .*);
+  dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.HADDR(HADDR[18:0]), .*);
+  dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.HADDR(HADDR[18:0]), .MemRWtim(MemRWboottim), 
+              .HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
 
   // memory-mapped I/O peripherals
   clint clint(.HADDR(HADDR[15:0]), .*);
-  gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
+  //gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
   uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
             .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
             .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); 
@@ -106,9 +109,9 @@ module uncore (
   // mux could also include external memory  
   // AHB Read Multiplexer
   assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) | 
-                     ({`XLEN{HSELGPIO}} & HREADGPIO) | ({`XLEN{HSELUART}} & HREADUART);
+                     ({`XLEN{HSELBootTim}} & HREADBootTim) | ({`XLEN{HSELUART}} & HREADUART);
-  assign HRESP = HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELGPIO & HRESPGPIO | HSELUART & HRESPUART;
+  assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELGPIO & HRESPGPIO | HSELUART & HRESPUART;
-  assign HREADY = HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELGPIO & HREADYGPIO | HSELUART & HREADYUART;
+  assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELGPIO & HREADYGPIO | HSELUART & HREADYUART;
 
   // Faults
   assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELGPIO | HSELUART);