forked from Github_Repos/cvw
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
This commit is contained in:
Ross Thompson
parent
c02141697d
commit
6bab454b17
@ -35,8 +35,8 @@ switch $argc {
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}
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}
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc -gDEBUG=1 work.testbench -o workopt
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vopt -fsmdebug +acc -gDEBUG=1 work.testbench -o workopt
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vsim workopt
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vsim workopt -fsmdebug
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do wave.do
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do wave.do
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@ -20,14 +20,14 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -129,19 +129,9 @@ add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/MemRWM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/AtomicM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/ReadDataW
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache -color Gray90 /testbench/dut/hart/dmem/CurrState
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemAccessM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/AtomicMaskedM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -184,66 +174,69 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDR
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITE
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZE
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HPROT
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add wave -noupdate -group csr -color Aquamarine -label {br executed} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]}
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HTRANS
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add wave -noupdate -group csr -color Aquamarine -label {br miss predicted} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]}
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group csr -childformat {{{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned}} /testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||||
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {12105831 ns} 0}
|
WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {4216 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 2
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 189
|
configure wave -valuecolwidth 189
|
||||||
@ -259,4 +252,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ns} {30754715 ns}
|
WaveRestoreZoom {4167 ns} {4406 ns}
|
||||||
|
|||||||
@ -52,11 +52,13 @@ module ahblite (
|
|||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
input logic [1:0] MemSizeM,
|
input logic [1:0] MemSizeM,
|
||||||
// Signals from MMU
|
// Signals from MMU
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
input logic MMUStall,
|
input logic MMUStall,
|
||||||
input logic [`XLEN-1:0] MMUPAdr,
|
input logic [`XLEN-1:0] MMUPAdr,
|
||||||
input logic MMUTranslate,
|
input logic MMUTranslate,
|
||||||
output logic [`XLEN-1:0] MMUReadPTE,
|
output logic [`XLEN-1:0] MMUReadPTE,
|
||||||
output logic MMUReady,
|
output logic MMUReady,
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
// Signals from PMA checker
|
// Signals from PMA checker
|
||||||
input logic DSquashBusAccessM, ISquashBusAccessF,
|
input logic DSquashBusAccessM, ISquashBusAccessF,
|
||||||
// Signals to PMA checker (metadata of proposed access)
|
// Signals to PMA checker (metadata of proposed access)
|
||||||
@ -114,14 +116,16 @@ module ahblite (
|
|||||||
// interface that might be used in place of the ahblite.
|
// interface that might be used in place of the ahblite.
|
||||||
always_comb
|
always_comb
|
||||||
case (BusState)
|
case (BusState)
|
||||||
IDLE: if (MMUTranslate) ProposedNextBusState = MMUTRANSLATE;
|
IDLE: /*if (MMUTranslate) ProposedNextBusState = MMUTRANSLATE;
|
||||||
else if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD;
|
else*/ if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD;
|
||||||
else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions
|
else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions
|
||||||
else if (MemWriteM) ProposedNextBusState = MEMWRITE;
|
else if (MemWriteM) ProposedNextBusState = MEMWRITE;
|
||||||
else if (InstrReadF) ProposedNextBusState = INSTRREAD;
|
else if (InstrReadF) ProposedNextBusState = INSTRREAD;
|
||||||
else ProposedNextBusState = IDLE;
|
else ProposedNextBusState = IDLE;
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
MMUTRANSLATE: if (~HREADY) ProposedNextBusState = MMUTRANSLATE;
|
MMUTRANSLATE: if (~HREADY) ProposedNextBusState = MMUTRANSLATE;
|
||||||
else ProposedNextBusState = IDLE;
|
else ProposedNextBusState = IDLE;
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD;
|
ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD;
|
||||||
else ProposedNextBusState = ATOMICWRITE;
|
else ProposedNextBusState = ATOMICWRITE;
|
||||||
ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE;
|
ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE;
|
||||||
@ -142,8 +146,8 @@ module ahblite (
|
|||||||
assign AtomicAccessM = (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
|
assign AtomicAccessM = (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
|
||||||
assign ExecuteAccessF = (ProposedNextBusState == INSTRREAD);
|
assign ExecuteAccessF = (ProposedNextBusState == INSTRREAD);
|
||||||
assign WriteAccessM = (ProposedNextBusState == MEMWRITE) || (ProposedNextBusState == ATOMICWRITE);
|
assign WriteAccessM = (ProposedNextBusState == MEMWRITE) || (ProposedNextBusState == ATOMICWRITE);
|
||||||
assign ReadAccessM = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == ATOMICREAD) ||
|
assign ReadAccessM = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == ATOMICREAD);// ||
|
||||||
(ProposedNextBusState == MMUTRANSLATE);
|
// (ProposedNextBusState == MMUTRANSLATE);
|
||||||
|
|
||||||
// The PMA and PMP checkers can decide to squash the access
|
// The PMA and PMP checkers can decide to squash the access
|
||||||
assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState;
|
assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState;
|
||||||
@ -165,14 +169,16 @@ module ahblite (
|
|||||||
assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) ||
|
assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) ||
|
||||||
(ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
|
(ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
|
||||||
assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
|
assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
|
||||||
assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress;
|
//assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress;
|
||||||
|
assign #1 HADDR = AccessAddress;
|
||||||
generate
|
generate
|
||||||
if (`XLEN == 32) assign PTESize = 3'b010; // in rv32, PTEs are 4 bytes
|
if (`XLEN == 32) assign PTESize = 3'b010; // in rv32, PTEs are 4 bytes
|
||||||
else assign PTESize = 3'b011; // in rv64, PTEs are 8 bytes
|
else assign PTESize = 3'b011; // in rv64, PTEs are 8 bytes
|
||||||
endgenerate
|
endgenerate
|
||||||
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
||||||
assign #1 AccessSize = (GrantData) ? {1'b0, MemSizeM} : ISize;
|
assign #1 AccessSize = (GrantData) ? {1'b0, MemSizeM} : ISize;
|
||||||
assign #1 HSIZE = (MMUTranslate) ? PTESize : AccessSize;
|
//assign #1 HSIZE = (MMUTranslate) ? PTESize : AccessSize;
|
||||||
|
assign #1 HSIZE = AccessSize;
|
||||||
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
|
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
|
||||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
assign HPROT = 4'b0011; // not used; see Section 3.7
|
||||||
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
||||||
@ -188,7 +194,7 @@ module ahblite (
|
|||||||
// Route signals to Instruction and Data Caches
|
// Route signals to Instruction and Data Caches
|
||||||
// *** assumes AHBW = XLEN
|
// *** assumes AHBW = XLEN
|
||||||
|
|
||||||
assign MMUReady = (BusState == MMUTRANSLATE && HREADY);
|
//assign MMUReady = (BusState == MMUTRANSLATE && HREADY);
|
||||||
|
|
||||||
assign InstrRData = HRDATA;
|
assign InstrRData = HRDATA;
|
||||||
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
||||||
@ -196,7 +202,7 @@ module ahblite (
|
|||||||
// *** Bracker 6/5/21: why is this W stage?
|
// *** Bracker 6/5/21: why is this W stage?
|
||||||
assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) ||
|
assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) ||
|
||||||
((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE));
|
((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE));
|
||||||
assign MMUReadPTE = HRDATA;
|
//assign MMUReadPTE = HRDATA;
|
||||||
// Carefully decide when to update ReadDataW
|
// Carefully decide when to update ReadDataW
|
||||||
// ReadDataMstored holds the most recent memory read.
|
// ReadDataMstored holds the most recent memory read.
|
||||||
// We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
|
// We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
|
||||||
|
|||||||
@ -195,7 +195,7 @@ module lsu (
|
|||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
// Data stall
|
// Data stall
|
||||||
assign DataStall = CurrState != STATE_READY;
|
assign DataStall = (CurrState == STATE_FETCH) || (CurrState == STATE_FETCH_AMO);
|
||||||
|
|
||||||
// Ross Thompson April 22, 2021
|
// Ross Thompson April 22, 2021
|
||||||
// for now we need to handle the issue where the data memory interface repeately
|
// for now we need to handle the issue where the data memory interface repeately
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user