forked from Github_Repos/cvw
added input enables and improved forwarding
This commit is contained in:
Katherine Parry
parent
e8c9830b88
commit
67c99d3d1a
@ -46,6 +46,8 @@ module fctrl (
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output logic [2:0] FrmM, // FP rounding mode
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output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic DivStartE, // Start division or squareroot
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output logic XEnE, YEnE, ZEnE,
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output logic YEnForwardE, ZEnForwardE,
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output logic FWriteIntE, FWriteIntM, // Write to integer register
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output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
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output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
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@ -173,23 +175,18 @@ module fctrl (
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assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
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// // signals to help readability
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// assign IntToFp = OpCtrl[2];
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// assign CvtOp = (PostProcSelE == 2'b00)&(FResSelE == 2'b01);
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// assign FmaOp = (PostProcSelE == 2'b10)&(FResSelE == 2'b01);
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// assign Sqrt = OpCtrl[0];
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// // is there an input of infinity or NaN being used
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// assign InfIn = (XInf&~(IntToFp&CvtOp))|(YInf&~CvtOp)|(ZInf&FmaOp);
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// assign NaNIn = (XNaN&~(IntToFp&CvtOp))|(YNaN&~CvtOp)|(ZNaN&FmaOp);
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// // enables:
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// // X - all except int->fp, store, load, mv int->fp
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// // Y - all except cvt, mv, load, class
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// // Z - fma ops only
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// assign XEnE = ;
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// assign YEnE = ~((FResSel==2'b10));
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// assign ZEnE = FmaOp&~OpCtrlE[2];
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// enables:
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// X - all except int->fp, store, load, mv int->fp
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// Y - all except cvt, mv, load, class
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// Z - fma ops only
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// load/store mv int->fp cvt int->fp
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assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2]));
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// load/class mv cvt
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assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&(PostProcSelE==2'b00)));
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assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]);
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assign YEnForwardE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&(PostProcSelE==2'b00)));
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assign ZEnForwardE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&~OpCtrlE[2];
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// Final Res Sel:
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// fp int
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@ -35,6 +35,7 @@ module fhazard(
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input logic FRegWriteM, FRegWriteW, // is the fp register being written to
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input logic [4:0] RdM, RdW, // the adress being written to
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input logic [1:0] FResSelM, // the result being selected
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input logic XEnE, YEnE, ZEnE,
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output logic FStallD, // stall the decode stage
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output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value
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);
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@ -47,33 +48,34 @@ module fhazard(
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ForwardZE = 2'b00; // choose FRD3E
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FStallD = 0;
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//*** this hazard unit is waiting for all three inputs, change so that if an input isnt used then don't wait
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// if the needed value is in the memory stage - input 1
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if ((Adr1E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W
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if(XEnE)
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if ((Adr1E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W
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// if the needed value is in the memory stage - input 2
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if ((Adr2E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W
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if(YEnE)
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if ((Adr2E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W
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// if the needed value is in the memory stage - input 3
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if ((Adr3E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W
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if(ZEnE)
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if ((Adr3E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W
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end
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@ -37,7 +37,6 @@ module flags(
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input logic NaNIn, // is a NaN input being used
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input logic [`FMTBITS-1:0] OutFmt, // output format
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input logic XZero, YZero, // inputs are zero
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input logic XNaN, YNaN, // inputs are NaN
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input logic Sqrt, // Sqrt?
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input logic ToInt, // convert to integer
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input logic IntToFp, // convert integer to floating point
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@ -153,11 +152,11 @@ module flags(
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// | | | | or the res rounds up out of bounds
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// | | | | and the res didn't underflow
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// | | | | |
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assign IntInvalid = XNaN|XInf|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
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assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
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// |
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// or when the positive res rounds up out of range
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assign SigNaN = (XSNaN&~(IntToFp&CvtOp)) | (YSNaN&~CvtOp) | (ZSNaN&FmaOp);
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assign FmaInvalid = ((XInf | YInf) & ZInf & (FmaPs ^ FmaAs) & ~XNaN & ~YNaN) | (XZero & YInf) | (YZero & XInf);
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assign FmaInvalid = ((XInf | YInf) & ZInf & (FmaPs ^ FmaAs) & ~NaNIn) | (XZero & YInf) | (YZero & XInf);
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assign DivInvalid = ((XInf & YInf) | (XZero & YZero))&~Sqrt | (Xs&Sqrt);
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assign Invalid = SigNaN | (FmaInvalid&FmaOp) | (DivInvalid&DivOp);
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@ -73,6 +73,8 @@ module fpu (
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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logic IllegalFPUInstrM;
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logic XEnE, YEnE, ZEnE;
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logic YEnForwardE, ZEnForwardE;
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// regfile signals
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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@ -163,8 +165,8 @@ module fpu (
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// calculate FP control signals
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .InstrD,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.reset, .clk, .IllegalFPUInstrD, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
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.DivStartE, .FWriteIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM,
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.reset, .clk, .IllegalFPUInstrD, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE,
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.DivStartE, .FWriteIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
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.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .Adr1E, .Adr2E, .Adr3E);
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// FP register file
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@ -193,7 +195,7 @@ module fpu (
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// Hazard unit for FPU
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// - determines if any forwarding or stalls are needed
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fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM,
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.FStallD, .ForwardXE, .ForwardYE, .ForwardZE);
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.XEnE, .YEnE(YEnForwardE), .ZEnE(ZEnForwardE), .FStallD, .ForwardXE, .ForwardYE, .ForwardZE);
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// forwarding muxs
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mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE);
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@ -233,11 +235,11 @@ module fpu (
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// - splits FP inputs into their various parts
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// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
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unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE),
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.Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE),
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.XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE),
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.Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
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.XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE),
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.YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XDenorm(XDenormE), .ZDenorm(ZDenormE),
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.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE),
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.ZInf(ZInfE), .XExpMax(XExpMaxE));
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.ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE));
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// fused multiply add
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// - fadd/fsub
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@ -135,8 +135,8 @@ module postprocess (
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assign Sqrt = OpCtrl[0];
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// is there an input of infinity or NaN being used
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assign InfIn = (XInf&~(IntToFp&CvtOp))|(YInf&~CvtOp)|(ZInf&FmaOp);
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assign NaNIn = (XNaN&~(IntToFp&CvtOp))|(YNaN&~CvtOp)|(ZNaN&FmaOp);
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assign InfIn = XInf|YInf|ZInf;
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assign NaNIn = XNaN|YNaN|ZNaN;
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// choose the ouptut format depending on the opperation
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// - fp -> fp: OpCtrl contains the percision of the output
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@ -219,7 +219,7 @@ module postprocess (
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flags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero,
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.Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
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.XNaN, .YNaN, .NaNIn, .FmaAs, .FmaPs, .R, .IntInvalid, .DivByZero,
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.NaNIn, .FmaAs, .FmaPs, .R, .IntInvalid, .DivByZero,
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.UfL, .S, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
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.Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg);
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@ -280,14 +280,14 @@ module specialcase(
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// other: 32 bit unsinged res should be sign extended as if it were a signed number
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always_comb
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if(Signed)
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if(Xs&~XNaN) // signed negitive
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if(Xs&~NaNIn) // signed negitive
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if(Int64) OfIntRes = {1'b1, {`XLEN-1{1'b0}}};
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else OfIntRes = {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
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else // signed positive
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if(Int64) OfIntRes = {1'b0, {`XLEN-1{1'b1}}};
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else OfIntRes = {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
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else
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if(Xs&~XNaN) OfIntRes = {`XLEN{1'b0}}; // unsigned negitive
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if(Xs&~NaNIn) OfIntRes = {`XLEN{1'b0}}; // unsigned negitive
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else OfIntRes = {`XLEN{1'b1}}; // unsigned positive
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@ -31,6 +31,7 @@
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module unpack (
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input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
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input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
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input logic XEn, YEn, ZEn,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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@ -46,15 +47,15 @@ module unpack (
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logic XFracZero, YFracZero, ZFracZero; // is the fraction zero
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logic YExpMax, ZExpMax; // is the exponent all 1s
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unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm),
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unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
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.NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
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.Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
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unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym),
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unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
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.NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
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.Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
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unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm),
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unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
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.NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
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.Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
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// is the input denormalized
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@ -30,7 +30,7 @@
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module unpackinput (
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input logic [`FLEN-1:0] In, // inputs from register file
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// input logic En, // enable the input
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input logic En, // enable the input
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input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
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output logic Sgn, // sign bits of XYZ
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output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision)
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@ -263,8 +263,8 @@ module unpackinput (
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// Output logic
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assign FracZero = ~|Frac; // is the fraction zero?
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assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if denormal or zero) to create the significand
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assign NaN = (ExpMax & ~FracZero)|BadNaNBox; // is the input a NaN?
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assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
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assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
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assign Inf = ExpMax & FracZero; // is the input infinity?
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assign Inf = ExpMax & FracZero &En; // is the input infinity?
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assign Zero = ~ExpNonZero & FracZero; // is the input zero?
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endmodule
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@ -66,9 +66,9 @@ module testbenchfp;
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logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic XSgn, YSgn, ZSgn; // sign of the inputs
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logic [`NE-1:0] XExp, YExp, ZExp; // exponent of the inputs
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logic [`NF:0] XMan, YMan, ZMan; // mantissas of the inputs
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logic Xs, Ys, Zs; // sign of the inputs
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logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
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logic XNaN, YNaN, ZNaN; // is the input NaN
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logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
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logic XDenorm, ZDenorm; // is the input denormalized
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@ -99,7 +99,7 @@ module testbenchfp;
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logic [`NE+1:0] Se;
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logic ZmSticky;
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logic KillProd;
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logic [$clog2(3*`NF+7)-1:0] NCnt;
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logic [$clog2(3*`NF+7)-1:0] SCnt;
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logic [3*`NF+5:0] Sm;
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logic InvA;
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logic NegSum;
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@ -650,14 +650,14 @@ module testbenchfp;
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// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
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readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
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.XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal),
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.XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal),
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.XManE(XMan), .YManE(YMan), .ZManE(ZMan), .DivStart,
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.XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN),
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.XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN),
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.XDenormE(XDenorm), .ZDenormE(ZDenorm),
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.XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero),
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.XInfE(XInf), .YInfE(YInf), .ZInfE(ZInf), .XExpMaxE(XExpMax),
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.Xs, .Ys, .Zs, .Unit(UnitVal),
|
||||
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
|
||||
.Xm, .Ym, .Zm, .DivStart,
|
||||
.XNaN, .YNaN, .ZNaN,
|
||||
.XSNaN, .YSNaN, .ZSNaN,
|
||||
.XDenorm, .ZDenorm,
|
||||
.XZero, .YZero, .ZZero,
|
||||
.XInf, .YInf, .ZInf, .XExpMax,
|
||||
.X, .Y, .Z);
|
||||
|
||||
|
||||
@ -673,34 +673,34 @@ module testbenchfp;
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// instantiate devices under test
|
||||
fma fma(.Xs(XSgn), .Ys(YSgn), .Zs(ZSgn),
|
||||
.Xe(XExp), .Ye(YExp), .Ze(ZExp),
|
||||
.Xm(XMan), .Ym(YMan), .Zm(ZMan),
|
||||
fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
|
||||
.Xe(Xe), .Ye(Ye), .Ze(Ze),
|
||||
.Xm(Xm), .Ym(Ym), .Zm(Zm),
|
||||
.XZero, .YZero, .ZZero, .Ss, .Se,
|
||||
.FOpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .NCnt, .As, .Ps,
|
||||
.OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps,
|
||||
.Pe, .ZmSticky, .KillProd);
|
||||
|
||||
postprocess postprocess(.Xs(XSgn), .Ys(YSgn), .PostProcSel(UnitVal[1:0]),
|
||||
.Ze(ZExp), .ZDenorm(ZDenorm), .FOpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
|
||||
.Xm(XMan), .Ym(YMan), .Zm(ZMan), .CvtCe(CvtCalcExpE), .DivS(DivSticky), .FmaSs(Ss),
|
||||
postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
|
||||
.Ze(Ze), .ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
|
||||
.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivS(DivSticky), .FmaSs(Ss),
|
||||
.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResDenormUf(CvtResDenormUfE),
|
||||
.XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE),
|
||||
.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
|
||||
.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
|
||||
.FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se),
|
||||
.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaNCnt(NCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
|
||||
.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
|
||||
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
|
||||
|
||||
fcvt fcvt (.Xs(XSgn), .Xe(XExp), .Xm(XMan), .Int(SrcA), .ToInt(WriteIntVal),
|
||||
.XZero(XZero), .XDenorm(XDenorm), .FOpCtrl(OpCtrlVal), .IntZero,
|
||||
fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
|
||||
.XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero,
|
||||
.Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
|
||||
fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp),
|
||||
.XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), .CmpIntResE(CmpRes),
|
||||
.XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpFpResE(FpCmpRes));
|
||||
divsqrt divsqrt(.clk, .reset, .FmtE(ModFmt), .XManE(XMan), .YManE(YMan), .XExpE(XExp), .YExpE(YExp),
|
||||
fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye,
|
||||
.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
|
||||
.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
|
||||
divsqrt divsqrt(.clk, .reset, .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye),
|
||||
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart),
|
||||
.StallE(1'b0), .StallM(1'b0), .DivStickyM(DivSticky), .DivBusy, .DivCalcExpM(DivCalcExp),
|
||||
.EarlyTermShiftM(EarlyTermShift), .QuotM(Quot), .DivDone);
|
||||
.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
|
||||
.EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone);
|
||||
|
||||
assign CmpFlg[3:0] = 0;
|
||||
|
||||
@ -868,10 +868,10 @@ end
|
||||
|
||||
// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
|
||||
// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
|
||||
else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res[`XLEN-1:0] === (`XLEN)'(0))) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
|
||||
(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
|
||||
(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
errors += 1;
|
||||
$display("There is an error in %s", Tests[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
@ -924,18 +924,19 @@ module readvectors (
|
||||
output logic [`FLEN-1:0] Ans,
|
||||
output logic [`XLEN-1:0] SrcA,
|
||||
output logic [4:0] AnsFlg,
|
||||
output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
|
||||
output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
|
||||
output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN
|
||||
output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN
|
||||
output logic XDenormE, ZDenormE, // is XYZ denormalized
|
||||
output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero
|
||||
output logic XInfE, YInfE, ZInfE, // is XYZ infinity
|
||||
output logic XExpMaxE,
|
||||
output logic Xs, Ys, Zs, // sign bits of XYZ
|
||||
output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
|
||||
output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
|
||||
output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
|
||||
output logic XDenorm, ZDenorm, // is XYZ denormalized
|
||||
output logic XZero, YZero, ZZero, // is XYZ zero
|
||||
output logic XInf, YInf, ZInf, // is XYZ infinity
|
||||
output logic XExpMax,
|
||||
output logic DivStart,
|
||||
output logic [`FLEN-1:0] X, Y, Z
|
||||
);
|
||||
logic XEn, YEn, ZEn;
|
||||
|
||||
// apply test vectors on rising edge of clk
|
||||
// Format of vectors Inputs(1/2/3)_AnsFlg
|
||||
@ -1257,8 +1258,12 @@ module readvectors (
|
||||
endcase
|
||||
end
|
||||
|
||||
unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE,
|
||||
.XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE,
|
||||
.XDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE,
|
||||
.XExpMaxE);
|
||||
assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
|
||||
assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT));
|
||||
assign ZEn = (Unit == `FMAUNIT);
|
||||
|
||||
unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
|
||||
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
||||
.XDenorm, .ZDenorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
||||
.XEn, .YEn, .ZEn, .XExpMax);
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user