forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Kip Macsai-Goren
commit
66fcb2bffe
@ -211,8 +211,8 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CAdrD}
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add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
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add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
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@ -288,7 +288,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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@ -197,7 +197,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
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add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
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add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
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@ -254,7 +254,7 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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@ -881,7 +881,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UnalignedNext
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextEPCM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextCauseM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextMtvalM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIP_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIE_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIP_REGW
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@ -896,7 +896,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/reset
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRMWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRSWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/ExtIntM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/TimerIntM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SwIntM
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@ -959,7 +959,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/count
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/LoadStallD
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRMWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/PrivilegeModeW
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRWriteValM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
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@ -1004,7 +1004,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/reset
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||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMWriteM
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||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTrapM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSCAdrM
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||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextEPCM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextCauseM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextMtvalM
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@ -1114,7 +1114,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/reset
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||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STrapM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextEPCM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextCauseM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextMtvalM
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@ -1188,7 +1188,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/reset
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTrapM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextEPCM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextCauseM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextMtvalM
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@ -1204,7 +1204,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/clk
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/reset
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUWriteM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSCAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRWriteValM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUReadValM
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add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/SetFflagsM
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@ -1,5 +1,5 @@
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onerror {resume}
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quietly virtual signal -install /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy { (context /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy )&{LRUWriteEn ,RAdr }} lru_enable_addr
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quietly virtual signal -install /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy { (context /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy )&{LRUWriteEn ,CAdr }} lru_enable_addr
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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@ -245,13 +245,13 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/lru_enable_addr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayEnc
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/RAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/CAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ReplacementBits[0]}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ReplacementBits
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LineReplacementBits
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||||
@ -325,7 +325,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
@ -349,7 +349,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victi
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelEvict
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
|
||||
14
pipelined/src/cache/cache.sv
vendored
14
pipelined/src/cache/cache.sv
vendored
@ -70,7 +70,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
localparam FlushAdrThreshold = NUMLINES - 1;
|
||||
|
||||
logic SelAdr;
|
||||
logic [SETLEN-1:0] RAdr;
|
||||
logic [SETLEN-1:0] CAdr;
|
||||
logic [LINELEN-1:0] LineWriteData;
|
||||
logic ClearValid;
|
||||
logic ClearDirty;
|
||||
@ -103,7 +103,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
|
||||
logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
|
||||
logic SelBusBuffer;
|
||||
logic SRAMEnable;
|
||||
logic ce;
|
||||
|
||||
localparam LOGLLENBYTES = $clog2(WORDLEN/8);
|
||||
localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN;
|
||||
@ -116,23 +116,23 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
// Read Path
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls
|
||||
// Choose read address (CAdr). Normally use NextAdr, but use PAdr during stalls
|
||||
// and FlushAdr when handling D$ flushes
|
||||
// The icache must update to the newest PCNextF on flush as it is probably a trap. Trap
|
||||
// sets PCNextF to XTVEC and the icache must start reading the instruction.
|
||||
mux3 #(SETLEN) AdrSelMux(
|
||||
.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
|
||||
.s({SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))}), .y(RAdr));
|
||||
.s({SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))}), .y(CAdr));
|
||||
|
||||
// Array of cache ways, along with victim, hit, dirty, and read merging logic
|
||||
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE)
|
||||
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask,
|
||||
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
|
||||
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
|
||||
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,
|
||||
.Invalidate(InvalidateCache));
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
|
||||
.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid);
|
||||
.clk, .reset, .ce, .HitWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid);
|
||||
end else assign VictimWay = 1'b1; // one hot.
|
||||
assign CacheHit = | HitWay;
|
||||
assign VictimDirty = | VictimDirtyWay;
|
||||
@ -217,6 +217,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelBusBuffer,
|
||||
.InvalidateCache,
|
||||
.SRAMEnable,
|
||||
.ce,
|
||||
.LRUWriteEn);
|
||||
endmodule
|
||||
|
||||
6
pipelined/src/cache/cacheLRU.sv
vendored
6
pipelined/src/cache/cacheLRU.sv
vendored
@ -35,7 +35,7 @@ module cacheLRU
|
||||
input logic clk, reset, ce,
|
||||
input logic [NUMWAYS-1:0] HitWay,
|
||||
output logic [NUMWAYS-1:0] VictimWay,
|
||||
input logic [SETLEN-1:0] RAdr,
|
||||
input logic [SETLEN-1:0] CAdr,
|
||||
input logic LRUWriteEn, SetValid);
|
||||
|
||||
logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0];
|
||||
@ -108,10 +108,10 @@ module cacheLRU
|
||||
if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
|
||||
if(ce) begin
|
||||
if (LRUWriteEn) begin
|
||||
LRUMemory[RAdr] <= NewLRU;
|
||||
LRUMemory[CAdr] <= NewLRU;
|
||||
CurrLRU <= #1 NewLRU;
|
||||
end else begin
|
||||
CurrLRU <= #1 LRUMemory[RAdr];
|
||||
CurrLRU <= #1 LRUMemory[CAdr];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
4
pipelined/src/cache/cachefsm.sv
vendored
4
pipelined/src/cache/cachefsm.sv
vendored
@ -72,7 +72,7 @@ module cachefsm
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic SelBusBuffer,
|
||||
output logic SRAMEnable);
|
||||
output logic ce);
|
||||
|
||||
logic resetDelay;
|
||||
logic AMO;
|
||||
@ -200,6 +200,6 @@ module cachefsm
|
||||
resetDelay;
|
||||
|
||||
assign SelBusBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY;
|
||||
assign SRAMEnable = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset;
|
||||
assign ce = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset;
|
||||
|
||||
endmodule // cachefsm
|
||||
|
||||
26
pipelined/src/cache/cacheway.sv
vendored
26
pipelined/src/cache/cacheway.sv
vendored
@ -36,7 +36,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
input logic ce,
|
||||
input logic reset,
|
||||
|
||||
input logic [$clog2(NUMLINES)-1:0] RAdr,
|
||||
input logic [$clog2(NUMLINES)-1:0] CAdr,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic [LINELEN-1:0] LineWriteData,
|
||||
input logic SetValidWay,
|
||||
@ -73,21 +73,23 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
logic SelTag;
|
||||
logic SelectedWriteWordEn;
|
||||
logic [LINELEN/8-1:0] FinalByteMask;
|
||||
logic SetValidEN;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Enable demux
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// If writing the whole line set all write enables to 1, else only set the correct word.
|
||||
assign SelectedWriteWordEn = SetValidWay | SetDirtyWay;// ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
|
||||
assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
|
||||
assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
|
||||
assign SetValidEN = SetValidWay & ~FlushStage;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Tag Array
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
|
||||
.addr(RAdr), .dout(ReadTag), .bwe('1),
|
||||
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~FlushStage));
|
||||
.addr(CAdr), .dout(ReadTag), .bwe('1),
|
||||
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
|
||||
|
||||
// AND portion of distributed tag multiplexer
|
||||
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
|
||||
@ -107,10 +109,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
|
||||
|
||||
for(words = 0; words < NUMSRAM; words++) begin: word
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr),
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(CAdr),
|
||||
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.we(SelectedWriteWordEn & ~FlushStage), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
|
||||
.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
|
||||
end
|
||||
|
||||
// AND portion of distributed read multiplexers
|
||||
@ -123,9 +125,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
|
||||
always_ff @(posedge clk) begin // Valid bit array,
|
||||
if (reset | Invalidate) ValidBits <= #1 '0;
|
||||
if(ce) begin Valid <= #1 ValidBits[RAdr];
|
||||
if (SetValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b0;
|
||||
if(ce) begin Valid <= #1 ValidBits[CAdr];
|
||||
if (SetValidEN) ValidBits[CAdr] <= #1 1'b1;
|
||||
else if (ClearValidWay & ~FlushStage) ValidBits[CAdr] <= #1 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -138,9 +140,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
|
||||
if(ce) begin
|
||||
Dirty <= #1 DirtyBits[RAdr];
|
||||
if (SetDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b0;
|
||||
Dirty <= #1 DirtyBits[CAdr];
|
||||
if (SetDirtyWay & ~FlushStage) DirtyBits[CAdr] <= #1 1'b1;
|
||||
else if (ClearDirtyWay & ~FlushStage) DirtyBits[CAdr] <= #1 1'b0;
|
||||
end
|
||||
end
|
||||
end else assign Dirty = 1'b0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user