Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

.gitignore

@@ -52,8 +52,16 @@ examples/asm/sumtest/sumtest
 examples/asm/example/example
 examples/C/sum/sum
 examples/C/fir/fir
+examples/fp/softfloat_demo/softfloat_demo
+examples/fp/fpcalc/fpcalc
+pipelined/src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
+linux/testvector-generation/genCheckpoint.gdb
+linux/testvector-generation/silencePipe
+linux/testvector-generation/silencePipe.control
+linux/testvector-generation/fixBinMem
+linux/testvector-generation/qemu-serial
 *.dtb
 synthDC/WORK
 synthDC/alib-52

Makefile

@@ -9,9 +9,9 @@ install:
 	cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
 	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
 	echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
-	cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
-	rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
-	ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	#cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
+	#rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	#ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
 	make -C pipelined/regression