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busybear: probably discovered bug in ahb code

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This commit is contained in:
Noah Boorstin 2021-03-01 20:56:04 +00:00
parent 965d48afe7
commit 62b441f3f5
3 changed files with 22 additions and 10 deletions
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10
wally-pipelined/regression/wally-busybear.do
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@ -59,12 +59,20 @@ add wave /testbench_busybear/lastCheckInstrF
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
add wave -divider add wave -divider
add wave -divider
add wave /testbench_busybear/dut/uncore/HSELBootTim add wave /testbench_busybear/dut/uncore/HSELBootTim
add wave /testbench_busybear/dut/uncore/HSELTim add wave /testbench_busybear/dut/uncore/HSELTim
add wave /testbench_busybear/dut/uncore/HREADTim add wave /testbench_busybear/dut/uncore/HREADTim
add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0 add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYTim add wave /testbench_busybear/dut/uncore/HREADYTim
add wave -divider
add wave /testbench_busybear/dut/uncore/HREADBootTim
add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYBootTim
add wave /testbench_busybear/dut/uncore/HADDR add wave /testbench_busybear/dut/uncore/HADDR
add wave /testbench_busybear/dut/uncore/HRESP
add wave /testbench_busybear/dut/uncore/HREADY
add wave /testbench_busybear/dut/uncore/HRDATA
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
@ -140,7 +148,7 @@ add wave /testbench_busybear/InstrWName
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW #add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
#add wave -divider #add wave -divider
##add ww ##add ww
#add wave -hex -r /testbench_busybear/* add wave -hex -r /testbench_busybear/*
# #
#-- Set Wave Output Items #-- Set Wave Output Items
#TreeUpdate [SetDefaultTree] #TreeUpdate [SetDefaultTree]

10
wally-pipelined/src/uncore/imem.sv
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@ -32,16 +32,16 @@ module imem (
output logic InstrAccessFaultF); output logic InstrAccessFaultF);
/* verilator lint_off UNDRIVEN */ /* verilator lint_off UNDRIVEN */
logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE-`TIMBASE)>>(1+`XLEN/32)]; logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE-`BOOTTIMBASE)>>(1+`XLEN/32)]; logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
/* verilator lint_on UNDRIVEN */ /* verilator lint_on UNDRIVEN */
logic [15:0] adrbits; logic [28:0] adrbits;
logic [`XLEN-1:0] rd; logic [`XLEN-1:0] rd;
// logic [15:0] rd2; // logic [15:0] rd2;
generate generate
if (`XLEN==32) assign adrbits = AdrF[17:2]; if (`XLEN==32) assign adrbits = AdrF[30:2];
else assign adrbits = AdrF[18:3]; else assign adrbits = AdrF[31:3];
endgenerate endgenerate
//assign #2 rd = RAM[adrbits]; // word aligned //assign #2 rd = RAM[adrbits]; // word aligned

12
wally-pipelined/testbench/testbench-busybear.sv
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@ -204,9 +204,10 @@ module testbench_busybear();
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change // this might need to change
always @(HWDATA or HADDR or HSIZE or HWRITE) begin //always @(HWDATA or HADDR or HSIZE or HWRITE) begin
#1; always @(negedge HWRITE) begin
if (HWRITE) begin //#1;
if ($time != 0) begin
if($feof(data_file_memW)) begin if($feof(data_file_memW)) begin
$display("no more memW data to read"); $display("no more memW data to read");
`ERROR `ERROR
@ -337,7 +338,9 @@ module testbench_busybear();
logic forcedInstr; logic forcedInstr;
logic [63:0] lastPCF; logic [63:0] lastPCF;
always @(dut.PCF or dut.hart.ifu.InstrF) begin always @(dut.PCF or dut.hart.ifu.InstrF) begin
if (~reset && dut.hart.ifu.InstrF !== {32{1'bx}}) begin if(~HWRITE) begin
#3;
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin
if (dut.PCF !== lastPCF) begin if (dut.PCF !== lastPCF) begin
lastCheckInstrF = CheckInstrF; lastCheckInstrF = CheckInstrF;
lastPC <= dut.PCF; lastPC <= dut.PCF;
@ -416,6 +419,7 @@ module testbench_busybear();
end end
lastPCF = dut.PCF; lastPCF = dut.PCF;
end end
end
end end
// Track names of instructions // Track names of instructions