forked from Github_Repos/cvw
removed rotate signal in datapath and instead packed into the new BALUControl Signal
- BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU
This commit is contained in:
Kevin Kim
parent
b6dd855395
commit
6295178073
@ -30,16 +30,16 @@
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [2:0] ALUSelect, // ALU mux select signal
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input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
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input logic [1:0] CompFlags, // Comparator flags
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input logic Rotate, // Perform Rotate Operation
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [2:0] ALUSelect, // ALU mux select signal
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input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
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input logic [1:0] CompFlags, // Comparator flags
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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@ -57,17 +57,23 @@ module alu #(parameter WIDTH=32) (
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logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [1:0] shASelect; // select signal for shifter source generation mux
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logic Rotate; // Indicates if it is Rotate instruction
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logic Mask; // Indicates if it is ZBS instruction
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logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Extract control signals from bitmanip ALUControl.
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assign {Rotate, Mask, PreShift} = BALUControl;
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// Pack control signals into shifter select
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assign shASelect = {W64,SubArith};
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if (`ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
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assign CondMaskB = (BSelect[0]) ? MaskB : B;
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assign CondMaskB = (Mask) ? MaskB : B;
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end else assign CondMaskB = B;
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// Sign/Zero extend mux
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@ -90,7 +96,7 @@ module alu #(parameter WIDTH=32) (
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if (`ZBA_SUPPORTED) begin: zbamuxes
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// Pre-Shift Mux
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always_comb
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case (Funct3[2:1] & {2{BSelect[3]}})
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case (Funct3[2:1] & {2{PreShift}})
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2'b00: CondShiftA = shA[WIDTH-1:0];
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2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add
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2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add
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@ -1,11 +1,11 @@
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///////////////////////////////////////////
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// controller.sv
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// bmuctrl.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 16 February 2023
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// Modified:
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//
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// Purpose: Top level B instrution controller module
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// Purpose: Top level B instruction decoder
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
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//
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@ -50,7 +50,8 @@ module bmuctrl(
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output logic [2:0] ZBBSelectE, // ZBB mux select signal
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output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
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output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage
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output logic RotateE // Indiciates if rotate instruction in Execute Stage
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output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage
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);
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logic [6:0] OpD; // Opcode in Decode stage
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@ -59,8 +60,10 @@ module bmuctrl(
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage
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logic RotateD; // Indicates if rotate instruction in Decode Stage
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`define BMUCTRLW 16
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logic MaskD; // Indicates if zbs instruction in Decode Stage
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logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
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logic [2:0] BALUControlD; // ALU Control signals for B instructions
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`define BMUCTRLW 18
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logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
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@ -74,92 +77,93 @@ module bmuctrl(
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// Main Instruction Decoder
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always_comb
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casez({OpD, Funct7D, Funct3D})
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_IllegalBitmanipInstrD
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
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// ZBS
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri
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17'b0010011_0100101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri (rv64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti
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17'b0010011_0100101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti (rv64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi
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17'b0010011_0110101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi (rv64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti
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17'b0010011_0010101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti (rv64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0; // sra, srai, srl, srli, sll, slli
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli
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// ZBC
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0; // ZBC instruction
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0_0_0; // ZBC instruction
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// ZBA
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0; // slli.uw
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_0_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0_0_0; // slli.uw
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// ZBB
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv32)
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv32)
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17'b0010011_0110001_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0011011_0110000_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // roriw
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // roriw
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0110000_001: if (Rs2D[2])
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // sign extend instruction
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // sign extend instruction
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else
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0; // count word instruction
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0_0_0; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0_0_0; // count word instruction
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17'b0111011_0000100_100: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0110011_0000100_100: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0; // xnor
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0_0_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0_0_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0_0_0; // xnor
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17'b0010011_0110101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_101: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // maxu
|
||||
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // min
|
||||
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // minu
|
||||
default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift
|
||||
BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction
|
||||
17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // orc.b
|
||||
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // max
|
||||
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // maxu
|
||||
default: BMUControlsD = {Funct3D, {14'b0}, {1'b1}}; // not B instruction or shift
|
||||
endcase
|
||||
|
||||
// Unpack Control Signals
|
||||
assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, IllegalBitmanipInstrD} = BMUControlsD;
|
||||
assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD;
|
||||
|
||||
// Pack BALUControl Signals
|
||||
assign BALUControlD = {RotateD, MaskD, PreShiftD};
|
||||
|
||||
// Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
|
||||
assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
|
||||
@ -167,5 +171,5 @@ module bmuctrl(
|
||||
|
||||
|
||||
// BMU Execute stage pipieline control register
|
||||
flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, RotateD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, RotateE});
|
||||
flopenrc#(15) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE});
|
||||
endmodule
|
||||
@ -60,7 +60,8 @@ module controller(
|
||||
output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
|
||||
output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
|
||||
output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage
|
||||
output logic RotateE, // Indicates if rotate instruction in Execute Stage
|
||||
output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
|
||||
|
||||
// Memory stage control signals
|
||||
input logic StallM, FlushM, // Stall, flush Memory stage
|
||||
output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write
|
||||
@ -223,7 +224,7 @@ module controller(
|
||||
|
||||
// BITMANIP Configuration Block
|
||||
if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
|
||||
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .RotateE);
|
||||
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE);
|
||||
if (`ZBA_SUPPORTED) begin
|
||||
// ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
|
||||
assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
|
||||
@ -242,7 +243,7 @@ module controller(
|
||||
assign BRegWriteE = 1'b0;
|
||||
assign BSubArithD = 1'b0;
|
||||
assign BComparatorSignedE = 1'b0;
|
||||
assign RotateE = 1'b0;
|
||||
assign BALUControlE = 3'b0;
|
||||
|
||||
assign sltD = (Funct3D == 3'b010);
|
||||
|
||||
|
||||
@ -48,7 +48,7 @@ module datapath (
|
||||
input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
|
||||
input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
|
||||
input logic [2:0] ZBBSelectE, // ZBB mux select signal
|
||||
input logic RotateE, // Indicates if Rotate instruction in Execute Stage
|
||||
input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
|
||||
output logic [1:0] FlagsE, // Comparison flags ({eq, lt})
|
||||
output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU
|
||||
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
|
||||
@ -60,7 +60,7 @@ module datapath (
|
||||
output logic [`XLEN-1:0] WriteDataM, // Write data in Memory stage
|
||||
// Writeback stage signals
|
||||
input logic StallW, FlushW, // Stall, flush Writeback stage
|
||||
input logic RegWriteW, IntDivW, // Write register file, integer divide instruction
|
||||
input logic RegWriteW, IntDivW, // Write register file, integer divide instruction
|
||||
input logic SquashSCW, // Squash a store conditional when a conflict arose
|
||||
input logic [2:0] ResultSrcW, // Select source of result to write back to register file
|
||||
input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result
|
||||
@ -113,7 +113,7 @@ module datapath (
|
||||
comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
|
||||
mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
|
||||
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
|
||||
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, RotateE, ALUResultE, IEUAdrE);
|
||||
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE);
|
||||
mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
|
||||
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
|
||||
|
||||
|
||||
@ -72,7 +72,7 @@ module ieu (
|
||||
output logic MDUStallD, CSRRdStallD, StoreStallD,
|
||||
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
|
||||
output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions
|
||||
output logic FenceM
|
||||
output logic FenceM
|
||||
);
|
||||
|
||||
logic [2:0] ImmSrcD; // Select type of immediate extension
|
||||
@ -87,7 +87,7 @@ module ieu (
|
||||
logic IntDivW; // Integer divide instruction
|
||||
logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
|
||||
logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage
|
||||
logic RotateE; // Indicates if Rotate Instruction in Execute Stage
|
||||
logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage
|
||||
|
||||
// Forwarding signals
|
||||
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers
|
||||
@ -101,7 +101,7 @@ controller c(
|
||||
.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
|
||||
.IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
|
||||
.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
|
||||
.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .MemRWM,
|
||||
.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
|
||||
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD);
|
||||
@ -109,7 +109,7 @@ controller c(
|
||||
datapath dp(
|
||||
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
|
||||
.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
|
||||
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .RotateE,
|
||||
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE,
|
||||
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user