random lint cleanup

wally-pipelined/src/fpu/fma.sv

@@ -468,9 +468,8 @@ module fma2(
     logic               Plus1, Minus1, CalcPlus1;   // do you add or subtract one for rounding
     logic               UfPlus1;                    // do you add one (for determining underflow flag)
     logic               Invalid,Underflow,Overflow; // flags
-    logic               ResultSgnTmp;   // the result's sign assuming the result is not zero
     logic               Guard, Round;   // bits needed to determine rounding
-    logic               UfRound, UfLSBNormSum;   // bits needed to determine rounding for underflow flag
+    logic               UfLSBNormSum;   // bits needed to determine rounding for underflow flag
    
     
 
@@ -497,7 +496,7 @@ module fma2(
     // round to nearest max magnitude
 
     fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgn, .SumExp,
-        .CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfRound, .UfLSBNormSum);
+        .CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfLSBNormSum);
 
 
 
@@ -688,7 +687,7 @@ module fmaround(
     output logic [`NF-1:0]  ResultFrac,         // Result fraction
     output logic [`NE-1:0]  ResultExp,          // Result exponent
     output logic            Sticky,             // sticky bit
-    output logic            Round, Guard, UfRound, UfLSBNormSum // bits needed to calculate rounding
+    output logic            Round, Guard, UfLSBNormSum // bits needed to calculate rounding
 );
     logic           LSBNormSum;         // bit used for rounding - least significant bit of the normalized sum
     logic           SubBySmallNum, UfSubBySmallNum;  // was there supposed to be a subtraction by a small number
@@ -696,6 +695,7 @@ module fmaround(
     logic           UfCalcPlus1, CalcMinus1;    // do you add or subtract on from the result
     logic [`FLEN:0] RoundAdd;           // how much to add to the result
     logic [`NF-1:0] NormSumTruncated;   // the normalized sum trimed to fit the mantissa
+    logic           UfRound;
 
     ///////////////////////////////////////////////////////////////////////////////
     // Rounding

wally-pipelined/src/ieu/ieu.sv

@@ -41,7 +41,6 @@ module ieu (
   output logic 		   MulDivE, W64E,
   output logic [2:0] 	   Funct3E,
   output logic [`XLEN-1:0] SrcAE, SrcBE,
-  output logic [4:0]    RdE,
   input logic 		   FWriteIntM,
 
   // Memory stage interface
@@ -81,6 +80,7 @@ module ieu (
   logic [2:0]  ResultSrcW;
   logic        TargetSrcE;
   logic        SCE;
+  logic [4:0]  RdE;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;

wally-pipelined/src/mmu/tlb.sv

@@ -98,7 +98,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
 
   // Sections of the page table entry
   logic [7:0]           PTEAccessBits;
-  logic [11:0]          PageOffset;
 
   logic [1:0]            HitPageType;
   logic                  CAMHit;

wally-pipelined/src/privileged/csrc.sv

@@ -71,8 +71,8 @@ module csrc #(parameter
   //HPMCOUNTER31H = 12'hC9F
 ) (
     input logic 	     clk, reset,
-    input logic 	     StallD, StallE, StallM, StallW,
-    input  logic             FlushD, FlushE, FlushM, FlushW,   
+    input logic 	     StallE, StallM, StallW,
+    input  logic       FlushE, FlushM, FlushW,   
     input logic 	     InstrValidM, LoadStallD, CSRMWriteM,
     input logic 	     BPPredDirWrongM,
     input logic 	     BTBPredPCWrongM,

wally-pipelined/src/uncore/clint.sv

@@ -42,11 +42,10 @@ module clint (
   logic        MSIP;
 
   logic [15:0] entry, entryd;
-  logic memread, memwrite;
+  logic memwrite;
   logic initTrans;
 
   assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
-  assign memread = initTrans & ~HWRITE;
   // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
   flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
   flopr #(16) entrydflop(HCLK, ~HRESETn, entry, entryd);

wally-pipelined/src/uncore/dtim.sv

@@ -46,7 +46,6 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
 
   logic        prevHREADYTim, risingHREADYTim;
   logic        initTrans;
-  logic [15:0] entry;
   logic        memwrite;
   logic [3:0]  busycount;