I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.

2022-03-25 13:10:31 -05:00 · 2022-03-25 13:10:31 -05:00 · 61c714ebe6
commit 61c714ebe6
parent 4ba0d1d662
1 changed files with 1 additions and 1 deletions
--- a/pipelined/src/privileged/csri.sv
+++ b/pipelined/src/privileged/csri.sv
@ -58,7 +58,7 @@ module csri #(parameter
  always_comb begin
    IntInM     = 0; 
    IntInM[11] = ExtIntM;                               // MEIP
-    IntInM[9]  = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP
+    IntInM[9]  = (ExtIntM & MIDELEG_REGW[9]);           // SEIP
    IntInM[7]  = TimerIntM;                             // MTIP
    IntInM[5]  = TimerIntM &  MIDELEG_REGW[5];          // STIP
    IntInM[3]  = SwIntM;                                // MSIP