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Moved privileged unit from datapath to hart

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This commit is contained in:
David Harris 2021-01-27 07:46:52 -05:00
parent e84fbd0a73
commit 616afaba69
7 changed files with 91 additions and 78 deletions
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27
wally-pipelined/src/controller.sv
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@ -35,6 +35,7 @@ module controller(
output logic [2:0] ImmSrcD, output logic [2:0] ImmSrcD,
input logic StallD, FlushD, input logic StallD, FlushD,
input logic IllegalCompInstrD, input logic IllegalCompInstrD,
output logic IllegalIEUInstrFaultD,
// Execute stage control signals // Execute stage control signals
input logic FlushE, input logic FlushE,
input logic [2:0] FlagsE, input logic [2:0] FlagsE,
@ -46,7 +47,7 @@ module controller(
// Memory stage control signals // Memory stage control signals
input logic FlushM, input logic FlushM,
output logic [1:0] MemRWM, output logic [1:0] MemRWM,
output logic CSRWriteM, PrivilegedM, IllegalInstrFaultM, output logic CSRWriteM, PrivilegedM,
output logic [2:0] Funct3M, output logic [2:0] Funct3M,
output logic RegWriteM, // for Hazard Unit output logic RegWriteM, // for Hazard Unit
// Writeback stage control signals // Writeback stage control signals
@ -55,10 +56,8 @@ module controller(
output logic [1:0] ResultSrcW, output logic [1:0] ResultSrcW,
output logic InstrValidW, output logic InstrValidW,
// Stall during CSRs // Stall during CSRs
output logic CSRWritePendingDEM, output logic CSRWritePendingDEM
// Exceptions );
input logic InstrAccessFaultF,
output logic InstrAccessFaultM);
// pipelined control signals // pipelined control signals
logic RegWriteD, RegWriteE; logic RegWriteD, RegWriteE;
@ -74,8 +73,6 @@ module controller(
logic [2:0] Funct3E; logic [2:0] Funct3E;
logic InstrValidE, InstrValidM; logic InstrValidE, InstrValidM;
logic PrivilegedD, PrivilegedE; logic PrivilegedD, PrivilegedE;
logic InstrAccessFaultD, InstrAccessFaultE;
logic IllegalInstrFaultD, IllegalInstrFaultE;
logic [18:0] ControlsD; logic [18:0] ControlsD;
logic PreIllegalInstrFaultD; logic PreIllegalInstrFaultD;
logic aluc3D; logic aluc3D;
@ -83,8 +80,6 @@ module controller(
logic BranchTakenE; logic BranchTakenE;
logic zeroE, ltE, ltuE; logic zeroE, ltE, ltuE;
// Decode stage pipeline control register and logic
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
// Main Instruction Decoder // Main Instruction Decoder
always_comb always_comb
@ -115,7 +110,7 @@ module controller(
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRWriteD, ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRWriteD,
PrivilegedD, PreIllegalInstrFaultD} = ControlsD & ~IllegalCompInstrD; PrivilegedD, PreIllegalInstrFaultD} = ControlsD & ~IllegalCompInstrD;
assign IllegalInstrFaultD = PreIllegalInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr assign IllegalIEUInstrFaultD = PreIllegalInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
// ALU Decoding // ALU Decoding
assign sltD = (Funct3D == 3'b010); assign sltD = (Funct3D == 3'b010);
@ -134,9 +129,9 @@ module controller(
endcase endcase
// Execute stage pipeline control register and logic // Execute stage pipeline control register and logic
floprc #(23) controlregE(clk, reset, FlushE, floprc #(21) controlregE(clk, reset, FlushE,
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRWriteD, PrivilegedD, IllegalInstrFaultD, InstrAccessFaultD, Funct3D, 1'b1}, {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRWriteD, PrivilegedD, Funct3D, 1'b1},
{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRWriteE, PrivilegedE, IllegalInstrFaultE, InstrAccessFaultE, Funct3E, InstrValidE}); {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRWriteE, PrivilegedE, Funct3E, InstrValidE});
// Branch Logic // Branch Logic
@ -158,9 +153,9 @@ module controller(
assign MemReadE = MemRWE[1]; assign MemReadE = MemRWE[1];
// Memory stage pipeline control register // Memory stage pipeline control register
floprc #(13) controlregM(clk, reset, FlushM, floprc #(11) controlregM(clk, reset, FlushM,
{RegWriteE, ResultSrcE, MemRWE, CSRWriteE, PrivilegedE, IllegalInstrFaultE, InstrAccessFaultE, Funct3E, InstrValidE}, {RegWriteE, ResultSrcE, MemRWE, CSRWriteE, PrivilegedE, Funct3E, InstrValidE},
{RegWriteM, ResultSrcM, MemRWM, CSRWriteM, PrivilegedM, IllegalInstrFaultM, InstrAccessFaultM, Funct3M, InstrValidM}); {RegWriteM, ResultSrcM, MemRWM, CSRWriteM, PrivilegedM, Funct3M, InstrValidM});
// Writeback stage pipeline control register // Writeback stage pipeline control register
floprc #(4) controlregW(clk, reset, FlushW, floprc #(4) controlregW(clk, reset, FlushW,

30
wally-pipelined/src/datapath.sv
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@ -50,28 +50,33 @@ module datapath (
// Memory stage signals // Memory stage signals
input logic FlushM, input logic FlushM,
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic CSRWriteM, PrivilegedM,
input logic InstrAccessFaultM, IllegalInstrFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
output logic InstrMisalignedFaultM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
output logic [31:0] InstrM,
output logic [`XLEN-1:0] SrcAM,
output logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] CSRReadValM,
input logic [`XLEN-1:0] PrivilegedNextPCM,
output logic [`XLEN-1:0] WriteDataM, ALUResultM, output logic [`XLEN-1:0] WriteDataM, ALUResultM,
output logic [`XLEN-1:0] InstrMisalignedAdrM,
input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] ReadDataM,
output logic [7:0] ByteMaskM, output logic [7:0] ByteMaskM,
output logic RetM, TrapM, input logic RetM, TrapM,
input logic [4:0] SetFflagsM,
input logic DataAccessFaultM, input logic DataAccessFaultM,
output logic InstrMisalignedFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, // *** eventually move these to the memory interface, along with memdp
output logic StoreMisalignedFaultM, StoreAccessFaultM,
// Writeback stage signals // Writeback stage signals
input logic FlushW, input logic FlushW,
input logic RegWriteW, input logic RegWriteW,
input logic [1:0] ResultSrcW, input logic [1:0] ResultSrcW,
input logic InstrValidW, input logic InstrValidW,
input logic FloatRegWriteW, input logic FloatRegWriteW,
output logic [2:0] FRM_REGW,
// Hazard Unit signals // Hazard Unit signals
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
output logic [4:0] RdE, RdM, RdW); output logic [4:0] RdE, RdM, RdW);
// Fetch stage signals // Fetch stage signals
logic [`XLEN-1:0] PCPlus2or4F; logic [`XLEN-1:0] PCPlus2or4F;
// Decode stage signals // Decode stage signals
@ -91,16 +96,8 @@ module datapath (
logic [`XLEN-1:0] WriteDataE; logic [`XLEN-1:0] WriteDataE;
logic [`XLEN-1:0] TargetBaseE; logic [`XLEN-1:0] TargetBaseE;
// Memory stage signals // Memory stage signals
logic [31:0] InstrM;
logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] SrcAM;
logic [`XLEN-1:0] ReadDataExtM; logic [`XLEN-1:0] ReadDataExtM;
logic [`XLEN-1:0] WriteDataFullM; logic [`XLEN-1:0] WriteDataFullM;
logic [`XLEN-1:0] CSRReadValM;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
// Writeback stage signals // Writeback stage signals
logic [`XLEN-1:0] ALUResultW; logic [`XLEN-1:0] ALUResultW;
logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] ReadDataW;
@ -156,9 +153,6 @@ module datapath (
memdp memdp(.AdrM(ALUResultM), .*); memdp memdp(.AdrM(ALUResultM), .*);
// Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*);
// Writeback stage pipeline register and logic // Writeback stage pipeline register and logic
floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW); floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW); floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW);

31
wally-pipelined/src/ieu.sv
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@ -33,8 +33,6 @@ module ieu (
output logic [7:0] ByteMaskM, output logic [7:0] ByteMaskM,
output logic [`XLEN-1:0] ALUResultM, WriteDataM, output logic [`XLEN-1:0] ALUResultM, WriteDataM,
input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] ReadDataM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrAccessFaultF,
input logic DataAccessFaultM, input logic DataAccessFaultM,
input logic [1:0] ForwardAE, ForwardBE, input logic [1:0] ForwardAE, ForwardBE,
input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW, input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
@ -42,12 +40,22 @@ module ieu (
output logic RegWriteM, output logic RegWriteM,
output logic MemReadE, output logic MemReadE,
output logic RegWriteW, output logic RegWriteW,
output logic CSRWriteM, PrivilegedM,
output logic CSRWritePendingDEM, output logic CSRWritePendingDEM,
output logic [31:0] InstrM,
output logic [`XLEN-1:0] SrcAM,
output logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] CSRReadValM,
input logic [`XLEN-1:0] PrivilegedNextPCM, // *** eentually move to ifu
output logic [`XLEN-1:0] InstrMisalignedAdrM,
output logic InstrMisalignedFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, // *** eventually move these to the memory interface, along with memdp
output logic StoreMisalignedFaultM, StoreAccessFaultM,
output logic IllegalIEUInstrFaultD,
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic FloatRegWriteW, output logic FloatRegWriteW,
output logic RetM, TrapM, output logic InstrValidW,
input logic RetM, TrapM,
input logic LoadStallD input logic LoadStallD
); );
@ -58,25 +66,12 @@ module ieu (
logic [2:0] ImmSrcD; logic [2:0] ImmSrcD;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [2:0] FlagsE; logic [2:0] FlagsE;
// logic PCSrcE;
logic [4:0] ALUControlE; logic [4:0] ALUControlE;
logic ALUSrcAE, ALUSrcBE; logic ALUSrcAE, ALUSrcBE;
// logic MemReadE;
// logic RegWriteM;
logic CSRWriteM;
logic PrivilegedM;
logic IllegalInstrFaultM; logic IllegalInstrFaultM;
logic InstrAccessFaultM;
logic [2:0] Funct3M; logic [2:0] Funct3M;
logic [1:0] ResultSrcW; logic [1:0] ResultSrcW;
// logic RegWriteW;
logic InstrValidW;
// logic LoadStallD;
// logic CSRWritePendingDEM;
logic InstrMisalignedFaultM;
// logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
logic TargetSrcE; logic TargetSrcE;
controller c(.*); controller c(.*);

4
wally-pipelined/src/privilegeDecoder.sv
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@ -28,7 +28,7 @@
module privilegeDecoder ( module privilegeDecoder (
input logic [31:20] InstrM, input logic [31:20] InstrM,
input logic PrivilegedM, IllegalInstrFaultInM, IllegalCSRAccessM, input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM,
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic STATUS_TSR, input logic STATUS_TSR,
output logic IllegalInstrFaultM, output logic IllegalInstrFaultM,
@ -47,7 +47,7 @@ module privilegeDecoder (
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001);
assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
assign IllegalInstrFaultM = IllegalInstrFaultInM | IllegalPrivilegedInstrM | IllegalCSRAccessM; assign IllegalInstrFaultM = IllegalIEUInstrFaultM | IllegalPrivilegedInstrM | IllegalCSRAccessM; // *** generalize this for other instructions
// *** initially, wfi and sfencevma are nop // *** initially, wfi and sfencevma are nop
// *** zfenci extension? // *** zfenci extension?

21
wally-pipelined/src/privileged.sv
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@ -37,13 +37,14 @@ module privileged (
output logic RetM, TrapM, output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic PrivilegedM, input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultInM, input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM, input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM, input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW output logic [2:0] FRM_REGW,
input logic FlushD, FlushE, FlushM, StallD
); );
logic [1:0] NextPrivilegeModeM, PrivilegeModeW; logic [1:0] NextPrivilegeModeM, PrivilegeModeW;
@ -54,7 +55,10 @@ module privileged (
// logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW; // logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW;
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
logic IllegalCSRAccessM, IllegalInstrFaultM; logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic IllegalInstrFaultM;
logic BreakpointFaultM, EcallFaultM; logic BreakpointFaultM, EcallFaultM;
logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM; logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM;
@ -81,6 +85,17 @@ module privileged (
// Control and Status Registers // Control and Status Registers
csr csr(.*); csr csr(.*);
// pipeline fault signals
flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
floprc #(2) faultregE(clk, reset, FlushE,
{IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD
{IllegalIEUInstrFaultE, InstrAccessFaultE});
floprc #(2) faultregM(clk, reset, FlushM,
{IllegalIEUInstrFaultE, InstrAccessFaultE},
{IllegalIEUInstrFaultM, InstrAccessFaultM});
endmodule endmodule

52
wally-pipelined/src/wallypipelinedhart.sv
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@ -38,28 +38,23 @@ module wallypipelinedhart (
input logic InstrAccessFaultF, input logic InstrAccessFaultF,
input logic DataAccessFaultM); input logic DataAccessFaultM);
/*
// logic [2:0] Funct3D;
// logic Funct7b5D;
// logic [6:0] OpD;
// logic [2:0] ImmSrcD;
// logic IllegalCompInstrD;
// logic [2:0] FlagsE;
// logic [4:0] ALUControlE;
// logic ALUSrcAE, ALUSrcBE;
// logic CSRWriteM;
// logic PrivilegedM;
// logic IllegalInstrFaultM;
logic InstrAccessFaultM;
logic [2:0] Funct3M;
logic [1:0] ResultSrcW;
logic InstrValidW;
logic InstrMisalignedFaultM;
*/
logic [1:0] ForwardAE, ForwardBE; logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, FlushD, FlushE, FlushM, FlushW; logic StallF, StallD, FlushD, FlushE, FlushM, FlushW;
logic RetM, TrapM; logic RetM, TrapM;
// new signals that must connect through DP
logic CSRWriteM, PrivilegedM;
logic [`XLEN-1:0] SrcAM;
logic [31:0] InstrM;
logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] CSRReadValM;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic InstrValidW;
logic InstrMisalignedFaultM, IllegalIEUInstrFaultD;
logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
logic PCSrcE; logic PCSrcE;
logic RegWriteM; logic RegWriteM;
logic MemReadE; logic MemReadE;
@ -82,8 +77,27 @@ module wallypipelinedhart (
hazard hzu(.*); // global stall and flush control hazard hzu(.*); // global stall and flush control
// Priveleged block operates in M and W stages, handling CSRs and exceptions // Priveleged block operates in M and W stages, handling CSRs and exceptions
// privileged priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*); privileged priv(.*);
/*
input logic clk, reset,
input logic CSRWriteM,
input logic [`XLEN-1:0] SrcAM,
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM,
output logic [`XLEN-1:0] CSRReadValM,
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultInM,
input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW
*/
// add FPU here, with SetFflagsM, FRM_REGW // add FPU here, with SetFflagsM, FRM_REGW
// presently stub out SetFlagsM and FloatRegWriteW // presently stub out SetFlagsM and FloatRegWriteW

2
wally-pipelined/testbench/testbench-imperas.sv
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@ -281,7 +281,7 @@ string tests32i[] = {
// check results // check results
always @(negedge clk) always @(negedge clk)
begin begin
if (dut.hart.ieu.dp.priv.EcallFaultM && if (dut.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
$display("Code ended with ecall with gp = 1"); $display("Code ended with ecall with gp = 1");
#60; // give time for instructions in pipeline to finish #60; // give time for instructions in pipeline to finish