Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev

src/ieu/alu.sv

@@ -68,7 +68,7 @@ module alu #(parameter WIDTH=32) (
  
   // SLT
   assign SLT = {{(WIDTH-1){1'b0}}, LT};
-  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
+  assign SLTU = {{(WIDTH-1){1'b0}}, LT};
  
   // Select appropriate ALU Result
   always_comb

src/ieu/controller.sv

@@ -99,7 +99,7 @@ module controller(
   logic        CSRWriteD, CSRWriteE;           // CSR write
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
   logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
-  logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
+  logic        ControlsD;                // Main Instruction Decoder control signals
   logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu
   logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
   logic        BranchTakenE;                   // Branch is taken

src/ieu/datapath.sv

@@ -101,7 +101,7 @@ module datapath (
   flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
   flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
   flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
+  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs1E);
   flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
   mux3  #(`XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);

testbench/testbench.sv

@@ -281,7 +281,7 @@ logic [3:0] dummy;
         // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
         if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
         else begin // hit reset threshold so we remove reset.
-          InReset = 0;
+          //InReset = 0; hmmm-I smell a wumpus
           ResetCount = 0;
         end
       end else begin