Minor change with the IFU in the decompress module, in the compressed instruction truth table.

The truth table is already fully covered, removed redundant last case checking
This commit is contained in:
Kevin Thomas 2023-04-05 10:27:52 -05:00
parent c21a5aaaf7
commit 5e5842893b

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@ -126,15 +126,15 @@ module decompress (
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
else // if (instr16[6:5] == 2'b11) else // if (instr16[6:5] == 2'b11)
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
else if (instr16[12:10] == 3'b111 & `XLEN > 32) else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
if (instr16[6:5] == 2'b00) if (instr16[6:5] == 2'b00)
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
else if (instr16[6:5] == 2'b01) else if (instr16[6:5] == 2'b01)
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
else begin // reserved else begin // reserved
IllegalCompInstrD = 1; IllegalCompInstrD = 1;
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
end end
// coverage off // coverage off
// are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits // are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
// This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other // This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other